verilog/nand_controller2
module nandc05_03b(
CLK,
RST,
LED_out,
CLED_out,
SW1,
SW1OUT,
SW2,
SW3,
SW3OUT,
SW4,
SW5,
RB,
STATUSLEDOUT,
LED_rdout,
LED_rdidout,
CLE,
CE,
WE,
ALE,
RE,
// NEXTOUT,
WP,
// TSW,
W_CYC_COUNT1,
CCERR,
ADCYCCNT,
/************** using for7seg*module*/
DATA,
SEVEN_SEG_DATA,
SEL,
EN,
/******************LCD display***********/
SHIFT_CLK,
rw,
rs,
en,
db,
//LCD display
sSHIFT_CLK,
srw,
srs,
sen,
sdb,
//ram
load,
store,
// ADDR,
// ewdata,
// erdata,
SCK,
INSTATUS,
//clk
LOCKED_OUT,
R_CYC_COUNT1
);
altpll1 U0(
.areset(RES_P),
.inclk0(CLK),
.c0(hclk),
.locked(hlocked)
);
parameter DWIDTH=36,AWIDTH=7,WORDS=128;//8 256 /3/6
ram1p1 U4(
.address(bramstorecnt),
.data(toramdata),
//.clock(rd_clk1),//hclk
.clock(cntw[0]),
.wren(toramen),//cntw[0
.rden(toramren),
// .outclock(toramren),
.q(fromramdata)
);
/**********************/
input wire CLK ;
input wire RST;
input SW1,SW2,SW3,SW4,SW5;
input RB ;
output LED_out ;
output CLED_out;
output[3:0] STATUSLEDOUT;
output LED_rdout;
output LED_rdidout;
output CLE;
output CE;
output WE;
output ALE;
output RE;
output WP;
output SW1OUT;
output SW3OUT;
output EN;
//output[7:0] W_CYC_COUNT1;
output[16:0] ADCYCCNT;
output CCERR;
output wire[15:0] W_CYC_COUNT1;
output wire[15:0] R_CYC_COUNT1;
/*7seg*/
output reg [7:0] SEVEN_SEG_DATA;
output[8:1] SEL;
output[3:0] INSTATUS;
/***********inout*****************/
inout[7:0] DATA;
// inout[15:0] DATA; //10/20
//wire sel;
reg wen;
//wire[7:0] dataout;
// reg[7:0] dataout;
// reg[7:0] din;
reg[7:0] din; //10/20 12/28 16
/*********************************/
wire LED_out ;
/*LCD display*/
//input[3:0] CUR;
output rw, rs ,SHIFT_CLK;
output en;
output [7:0] db;
//display2
output wire srw, srs ,sSHIFT_CLK;
output wire sen;
output wire[7:0] sdb;
/************/
output LOCKED_OUT;
//ram//
// output reg[7:0] SEVEN_SEG_DATA;
// output[4:1] SEL;
output SCK;
input load;
input store;
//input[DWIDTH-1:0] ewdata;
//output[DWIDTH-1:0] erdata;
reg[DWIDTH-1:0] ewdata;
reg[DWIDTH-1:0] erdata;
reg[DWIDTH-1:0] erdatanxt;
//(* ramstyle="M9K" *) reg[DWIDTH-1:0] ram[WORDS-1:0];
(* ramstyle="BLOCK" *) reg[DWIDTH-1:0] ram[WORDS-1:0];
reg[AWIDTH-1:0] addr;
reg[7:0] loadcnt;
reg[7:0] loadcntnxt;
reg[7:0] storecnt;
reg rsck;
reg [31:0] rsec_cnt ;//１秒作成用カウンタ
reg rsec1_flag ;//1秒のフラグ
reg rtoggle_flag ; //1秒ごとにトグルするフラグ
reg[3:0] enable_Seg;
reg[8:1] sel;
reg[7:0] seven_seg1_hold;
reg[7:0] seven_seg2_hold;
reg[7:0] seven_seg3_hold;
reg[7:0] seven_seg4_hold;
reg[7:0] seven_seg5_hold;
reg[7:0] seven_seg6_hold;
reg[7:0] seven_seg7_hold;
reg[7:0] seven_seg8_hold;
reg[7:0] seven_seg;
reg[3:0] enable_seg;
reg sck;
reg[3:0] seven_seg1_counter;
reg[3:0] seven_seg2_counter;
reg[3:0] seven_seg3_counter;
reg[3:0] seven_seg4_counter;
reg[3:0] seven_seg5_counter;
reg[3:0] seven_seg6_counter;
reg[3:0] seven_seg7_counter;
reg[3:0] seven_seg8_counter;
reg [31:0] sec_cnt ;//１秒作成用カウンタ
reg sec1_flag ;//1秒のフラグ
reg toggle_flag ; //1秒ごとにトグルするフラグ
reg [3:0] cur;//ステートレジスタ
reg [3:0] nxt;//ステート生成回路
reg [31:0] swchatcnt1;
reg swchatbuf1;
reg swchat1_flag;
reg swchat1_toggle;
reg sw1p;
reg [3:0] detcnt1;
reg sw1;
reg [31:0] swchatcnt2;
reg swchatbuf2;
reg sw2p;
reg [3:0] detcnt2;
reg sw2;
reg [31:0] swchatcnt3;
reg swchatbuf3;
reg [3:0] detcnt3;
reg sw3p;
reg sw3;
reg [31:0] swchatcnt4;
reg swchatbuf4;
reg [3:0] detcnt4;
reg sw4p;
reg sw4;
reg [31:0] swchatcnt5;
reg swchatbuf5;
reg [3:0] detcnt5;
reg sw5p;
reg sw5;
reg[31:0] chat_cnt;
reg chat_cnt_flag;
reg chat_cnt_toggle_flag;
reg normalout;
reg readidout;
reg readout;
reg writeout;
reg [31:0] rd_cnt1;
reg rd_cnt_flag1;
reg rd_clk1;
reg [15:0] rdid_cnt1;
reg rdid_cnt_flag1;
reg rdid_clk1;
reg rdidframe;
reg cle;
reg cen;
reg[7:0] errstatus;
// reg wen;
reg ale;
reg ren;
reg wp ;
reg [23:0] cntw;
reg [9:0] next; //7 3/8
reg [7:0] tsw;
//reg [15:0] tsw;
reg wenspan;
//status register
reg[7:0] status_reg;
reg[15:0]r_cyc_count1;
reg[15:0]w_cyc_count1;
//reg[15:0]c_cyc_count1;
reg[9:0]e_cyc_count1;
reg[9:0]ecyc;
//addr //
reg[7:0] addrs1;
reg[7:0] addrs2;
//addr start//
reg[7:0] addrs3;
reg[7:0] addrs4;
//addr end
reg[7:0] addre3;
reg[7:0] addre4;
//use for Display addr//
reg[7:0] addrp1;
reg[7:0] addrp2;
reg[7:0] addrp3;
reg[7:0] addrp4;
reg[11:0] caddrs1;
reg[7:0] wdatain;
reg[16:0] adcyc;
reg[16:0] adcyccnt;
reg[15:0] counterseg1;
reg[15:0] counterseg2;
reg[15:0] counterseg3;
reg[15:0] counterseg4;
reg[3:0] instatus;
reg[35:0] toramdata;
reg toramen;
wire[35:0] fromramdata;
reg toramren;
reg[15:0] bramstorecnt;
reg[15:0] bramstorecntoffset;
reg[15:0] bramstorecnttemp;
reg[15:0] bramstorecnttemp2;
reg[15:0] bramstorecntoffset2;
reg[15:0] bramstorecntoffset3;
reg[15:0] bramstorecnttemp3;
/**********************/
//PLL
wire RES_P;
wire hclk ;
wire hlocked;
/**********************/
//ram//
// parameter DWIDTH=36,AWIDTH=8,WORDS=256;
parameter rF50M000_cnt=32'h000001f4 ;
// parameter rF50M000_cnt=32'h00060000 ;
parameter selinit_value =8'b10000000;
//
// parameter F50M000_cnt=32'h02FAF080 ;//1秒ごとの変化
parameter F50M000_cnt=32'h017D7840 ;//0.5秒ごとの変化
//parameter F50M000_rdcnt=32'h000009c4;//0.00001sec 10/1doukaku 10/18 write動作確認
parameter F50M000_rdcnt=32'h00000003; ///12/14/a 5Mhz動作/0.1usec 10Mhz 5 11/25動作せず//19 12/12動作//1a 動作12/12 //25/12/10動作//30 1.02MHz 動作//
// parameter F50M000_rdcnt=32'h0007a120; //10/3
// parameter F50M000_rdcnt=32'h000f4240;
// parameter F50M000_rdcnt=32'h017d7840;
parameter swchatcntof = 32'h00bebc20;//64
//parameter swchantcntofsw1 = 32'h005f5e10; //0.125secシミュレーター用 write動作確認1 ff-100
parameter swchantcntofsw1 = 32'h00bebc20; //0.125secシミュレーター用 write動作確認1 ff-100
// parameter swchantcntofsw1 = 32'h0000000ff; //シミュレーター用 write動作確認1 ff-100
//parameter swchantcntofsw1 = 32'h000000ff;
// parameter swchantcntofsw2 = 32'h004c4b40; //44aa20 0.09 4c4b40 0.1sec
parameter swchantcntofsw2 = 32'h00bebc20; //98960 0.09 4c4b40 0.2sec
// parameter swchantcntofsw2 = 32'h00000064; //シミュレーター用 write動作確認1 64
// parameter swchantcntofsw3 = 32'h000009c4; //ff
parameter swchantcntofsw3 = 32'h0000927c0; //
// parameter swchantcntofsw3 = 32'h00000384;//44aa20/9c4 =708h 384h 1c2h
//parameter swchantcntofsw3 = 32'h00000064; //シミュレーター用 write動作確認1 64
/***********************/
parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
initial cur <=4'b0000;
initial toggle_flag <= 1'b1;
initial chat_cnt <=32'h00000000;
initial chat_cnt_flag <= 1'b1;
initial chat_cnt_toggle_flag <=1'b1;
initial sec_cnt <=32'h00000000;
initial sec1_flag <=1'b1;
initial rd_cnt1 <=32'h00000000;
initial rd_cnt_flag1 <= 1'b1;
initial rd_clk1 <= 1'b1;
//initial nxt <=2'b00;
//initial rdid_cnt1 <= 16'h0000;
// initial rdid_cnt_flag1 <=1'b1;
// initial rdid_clk1 <= 1'b1;
// initial rdidframe <=1'b1;
initial swchat1_flag<=1'b0;
initial swchat1_toggle<=1'b0;
initial swchatbuf1 <=1'b1;
initial swchatbuf2 <=1'b1;
initial swchatbuf3 <=1'b1;
initial swchatbuf4 <=1'b1;
initial detcnt1 <=4'b0000;
initial detcnt2 <=4'b0000;
initial detcnt3 <=4'b0000;
initial detcnt4 <=4'b0000;
initial detcnt5 <=4'b0000;
initial cle <= 1'b0;
initial cen <= 1'b1;
initial wen <= 1'b1;
initial ale <= 1'b0;
initial ren <= 1'b1;
initial wp <= 1'b1;
initial wenspan <= 1'b0;
initial cntw =24'h000000;
initial next = 10'b0000000000;
initial tsw = 8'hZZ;
//initial tsw = 16'bZZZZZZZZZZZZZZZZ;
initial din = 8'b00000000;
initial r_cyc_count1=16'h0000;
initial w_cyc_count1 =16'h0000;
//initial c_cyc_count1 =16'h0000;
initial e_cyc_count1 =10'h0000;
initial adcyccnt =17'b00000000000000000;
initial addrs1 =8'b00000000;
initial addrs2 =8'b00000000;
//initial addrs3 =8'b00001000;//10/18動作確認済
initial addrs3 =8'b00000000;
initial addrs4 =8'b00000000;
initial addre3 =8'b00000000;
initial addre4 =8'b00000000;
// initial caddrs1=12'd0256; //256:100h(256まで) //83fh 12'b1000 0011 1111 d2111
initial caddrs1=12'h7ff; //256:100h(256まで) //7ff 2047(2048byte) //83fh 12'b1000 0011 1111 d2111
initial adcyc=17'b00000000000000000;
// initial ecyc=10'b0000000101; //max 3ff
initial ecyc=10'h3ff; //max 3ff 1023
initial wdatain=8'b00000000;
initial storecnt=8'h00;
/********7seg **************/
//ram
initial loadcnt = 8'b00000000;//00000000
initial loadcntnxt = 8'b00000000;//00000000
initial instatus =4'b0000;
integer i;
initial begin
for(i=0;i<WORDS;i=i+1)
ram[i]=i;
end
initial rsck = 1'b0;
initial rsec1_flag =1'b0;
initial rtoggle_flag =1'b0;
initial rsec_cnt = 32'h00000000 ;
initial seven_seg1_counter = 4'h1;
initial seven_seg2_counter= 4'h2;
initial seven_seg3_counter= 4'h3;
initial seven_seg4_counter= 4'h4;
initial loadcnt = 8'b00000000;
//initial seven_seg1_hold =8'b1
initial toramen = 1'b0;
initial toramren = 1'b0;
initial bramstorecnt=16'h0000;
initial bramstorecntoffset=16'h0100;//20
initial bramstorecnttemp=16'h0000;
initial bramstorecntoffset2=16'h0200;//20
initial bramstorecntoffset3=16'h0600;//20
initial bramstorecnttemp2=16'h0000;
initial bramstorecnttemp3=16'h0000;
assign RES_P = ~RST;
assign LOCKEDOUT = hlocked;
always@(posedge hclk)
begin
if(rsec_cnt == rF50M000_cnt) begin //もし3300万回数えたらカウンタをリセットする
rsec_cnt <= 32'h00000000 ;
rsec1_flag <= 1'b1; //SEC1_FLAGに1をセットする
end else begin
rsec_cnt <= rsec_cnt + 1 ;
rsec1_flag <= 1'b0 ;
end
end
/**********************/
/*1秒検出部 */
/**********************/
always@(posedge hclk)
begin
if(rsec1_flag == 1'b1 )begin
rtoggle_flag <= !rtoggle_flag ;
end
end
/**********************/
/*出力部 */
/**********************/
always@*
begin
rsck <= ~rtoggle_flag;
end
/**********************/
/*
always@(posedge hclk)
begin
addr<=ADDR;
end
*/
/*
always @(negedge RST or posedge rsck )
begin
if(RST ==1'b0)
begin
storecnt <= 8'b00000000;
end else begin
if(store==1'b0) begin
// ram[storecnt] <= ewdata;
// erdata <= ram[storecnt];
// storecnt <= storecnt + 1;
end else if(load==1'b0)begin
erdata <= ram[loadcnt];
loadcnt <= loadcnt +1;
end
end
end
*/
always@(posedge rsck or negedge RST)begin
if(RST == 1'b0 )begin
enable_seg <= 4'b0000;
end else if(enable_seg ==4'b0111)begin
enable_seg <= 4'b0000;
end else begin
enable_seg <= enable_seg +1'b1;
end
end
always@(posedge rsck or negedge RST)begin
if(RST == 1'b0 )begin
sel <= selinit_value;
end else begin
sel[2] <= sel[1] ; //シフト動作を開始する
sel[3] <= sel[2] ; //シフト動作を開始する
sel[4] <= sel[3] ; //シフト動作を開始する
sel[5] <= sel[4] ;
sel[6] <= sel[5] ; //シフト動作を開始する
sel[7] <= sel[6] ; //シフト動作を開始する
sel[8] <= sel[7] ; //シフト動作を開始する
sel[1] <= sel[8] ;
end
end
assign SEL[8:1] = sel[8:1];
always@(negedge RST or posedge hclk)
begin if(RST ==1'b0)begin
seven_seg1_hold <=8'b00000110;
seven_seg2_hold <=8'b01011011;
//seven_seg3_hold <=8'b01001111;
//seven_seg4_hold <=8'b01100110;
seven_seg3_hold <=8'b00111111;
seven_seg4_hold <=8'b00111111;
seven_seg5_hold <=8'b01101101;
seven_seg6_hold <=8'b01111101;
seven_seg7_hold <=8'b00100111;
seven_seg8_hold <=8'b00111111;
end else begin
// case(seven_seg1_counter)
// case(erdata[3:0])
// case(adcyccnt[3:0])
//case(w_cyc_count1[3:0])
//case(errstatus[3:0])
case(toramdata[23:20])
4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg1_hold <= 8'b00000110;
endcase
//case(seven_seg2_counter)
// case(erdata[7:4])
//case(w_cyc_count1[7:4])
case(toramdata[27:24])
//case(errstatus[7:4])
4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg2_hold <= 8'b01011011;
endcase
//case(seven_seg3_counter)
//case(loadcnt[3:0])
// case(adcyccnt[11:8])
//case(w_cyc_count1[11:8])
case(toramdata[31:28])
//case(addrp2[3:0])
4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg3_hold <= 8'b01001111;
endcase
// case(seven_seg4_counter)
//case(loadcnt[7:4])
//case(adcyccnt[15:12])
//case(w_cyc_count1[15:12])
//case(addrp3[3:0])
case(toramdata[35:32])
4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg4_hold <= 8'b01100110;
endcase
case(fromramdata[23:20])
// case(adcyccnt[19:16])
//case(w_cyc_count1[3:0])
//case(addrp3[7:4])
4'b0000 : seven_seg5_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg5_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : seven_seg5_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg5_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg5_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg5_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg5_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg5_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg5_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg5_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg5_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg5_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg5_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg5_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg5_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg5_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg5_hold <= 8'b01101101;
endcase
//case(seven_seg2_counter)
// case(erdata[7:4])
// case(adcyccnt[23:20])
//case(w_cyc_count1[7:4])
case(fromramdata[27:24])
//case(addrp4[3:0])
4'b0000 : seven_seg6_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg6_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg6_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg6_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg6_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg6_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg6_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg6_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg6_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg6_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg6_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg6_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg6_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg6_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg6_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg6_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg6_hold <= 8'b01111101 ;
endcase
//case(seven_seg3_counter)
//case(loadcnt[3:0])
// case(adcyccnt[27:24])
//case(w_cyc_count1[11:8])
case(fromramdata[31:28])
//case(addrp4[7:4])
4'b0000 : seven_seg7_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg7_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : seven_seg7_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg7_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg7_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg7_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg7_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg7_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg7_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg7_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg7_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg7_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg7_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg7_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg7_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg7_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg7_hold <= 8'b00100111;
endcase
// case(seven_seg4_counter)
//case(loadcnt[7:4])
//case(adcyccnt[31:28])
//case(w_cyc_count1[15:12])
//case(addrp2[7:4])//固定low
case(fromramdata[35:32])
4'b0000 : seven_seg8_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg8_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg8_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg8_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg8_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg8_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg8_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg8_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg8_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg8_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg8_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg8_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg8_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg8_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg8_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg8_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg8_hold <= 8'b01111111;
endcase
end
end
always@*
begin
case(enable_seg)
// 2'b00: seven_seg<=~seven_seg4_hold;
4'b0000: SEVEN_SEG_DATA <= ~seven_seg8_hold;
4'b0001: SEVEN_SEG_DATA<=~seven_seg1_hold;
4'b0010: SEVEN_SEG_DATA<=~seven_seg2_hold;
4'b0011: SEVEN_SEG_DATA<=~seven_seg3_hold;
4'b0100: SEVEN_SEG_DATA<=~seven_seg4_hold;
4'b0101: SEVEN_SEG_DATA<=~seven_seg5_hold;
4'b0110: SEVEN_SEG_DATA<=~seven_seg6_hold;
4'b0111: SEVEN_SEG_DATA<=~seven_seg7_hold;
// default: SEVEN_SEG_DATA <= 8'b00000000;
endcase
end
//
/*
seg7_01_01 U1(
.hclk(hclk), //.signal bottom(signal top),
.DATA(DATA),
.RST(RST),
.SEVEN_SEG_DATA(SEVEN_SEG_DATA),
.SEL(SEL),
.EN(EN)
);
*/
/*************************/
/*************LCD display**************************/
lcd_sc1602_06_4b_01 U2( //.signal bottom(signal top),
//.hclk(hclk),
.CLK(hclk),
.DATA(DATA),
.RST(RST),
.CUR(cur),
.rw(rw),
.rs(rs),
.en(en),
.db(db),
.addrs1(addrp1),
.addrs2(addrp2),
.addrs3(addrp3),
.addrs4(addrp4),
.wdatain(wdatain),
.EN(EN),
.INSTATUS(instatus)
);
lcd_sc1602_06_4b_01ch01 U3( /////////////////////compare check display
//.hclk(hclk),
.CLK(hclk),
.DATA(DATA),
.RST(RST),
.CUR(cur),
.rw(srw),
.rs(srs),
.en(sen),
.db(sdb),
.addrs1(addrp1),
.addrs2(addrp2),
.addrs3(addrp3),
.addrs4(addrp4),
.wdatain(wdatain),
.EN(sEN),
.erdata(erdata),
.erdatanxt(erdatanxt),
.loadcnt(loadcnt),
.loadcntnxt(loadcntnxt)
);
//parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
//parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ReErsPrgCom=4'b1110;
always@(posedge hclk)
begin
if(sw1 || sw2 || sw3 || sw4)begin
adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}; //12/28
end else
if(cur==4'b0011 || cur ==4'b0110 || cur ==4'b0111)begin // READPAGE c change a change
if(adcyccnt[15:0]==16'h00)begin
addrp1<= r_cyc_count1[7:0];
addrp2<= r_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= r_cyc_count1[7:0];
addrp2<= r_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end else if(cur==4'b0100)begin //ERACE BLOCK achange
if(e_cyc_count1[9:0]==10'b0000000000)begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
{addrp4,addrp3}<={addrs4,addrs3}+{e_cyc_count1[9:0],6'b000000};
end
end else if(cur==4'b0101)begin //program page c change a change
if(adcyccnt[15:0]==16'h00)begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end else if(cur==4'b1000)begin //compare CHECK c cahge a chagen
if(adcyccnt[15:0]==16'h00)begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end else if(cur==4'b1001)begin //AdSel start old status was Addselect 1001
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3; //input start addr
addrp4<=addrs4; //input start addr
end else if(cur==4'b1010)begin //AdSel end
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addre3; //input end addr
addrp4<=addre4; //input end addr
end else if(cur==4'b1011)begin //Adcycl 1100
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
{addrp4,addrp3} <= adcyc[15:0];
end else if(cur==4'b1100)begin //Datainput 1010
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3; //input addr
addrp4<=addrs4; //input addr
end else if(cur==4'b1110)begin //ErsPrgCom 1110
if(instatus == 4'b1000 )begin //instatus /4'b1000 Read Page /4'b0001 Erase /4'b0010 Program /4'b0100 CompareCheck
if(adcyccnt[15:0]==16'h00)begin
addrp1<= r_cyc_count1[7:0];
addrp2<= r_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= r_cyc_count1[7:0];
addrp2<= r_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end else if(instatus == 4'b0001 )begin //instatus /4'b1000 Read Page /4'b0001 Erase /4'b0010 Program /4'b0100 CompareCheck
if(e_cyc_count1[9:0]==10'b0000000000)begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
{addrp4,addrp3}<={addrs4,addrs3}+{e_cyc_count1[9:0],6'b000000};
end
end else if(instatus == 4'b0010 || instatus == 4'b0100)begin
if(adcyccnt[15:0]==16'h00)begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end
end else begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3;
addrp4<=addrs4;
end
end
assign LED_out = toggle_flag ;
/******************************************************************************/
/*****************readcycle counter*******************************/
always@(posedge hclk)
begin
if(rd_cnt1 == F50M000_rdcnt) begin //もし3300万回数えたらカウンタをリセットする
rd_cnt1 <= 32'h00000000 ;
rd_cnt_flag1 <= 1'b1; //SEC1_FLAGに1をセットする
end else begin
rd_cnt1 <= rd_cnt1 + 1 ;
rd_cnt_flag1 <= 1'b0 ;
end
end
/**********************/
/*1秒検出部 */
/**********************/
always@(posedge hclk)
begin
if(rd_cnt_flag1 == 1'b1 )begin
rd_clk1 <= !rd_clk1 ;
end
end
/*****************^end readcycle counter*******************************/
/**********************/
/*LED出力部 */
/**********************/
// assign LED_rdout = rd_clk1 && rdidframe; //9/30
assign LED_rdout = rd_clk1 ;
/*************************************************/
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0)
cur <= NORMAL;
else
cur <= nxt;
end
always@(posedge hclk)
begin
if(chat_cnt == swchatcntof) begin //
chat_cnt <= 32'h00000000 ;
chat_cnt_flag <= 1'b1; //SEC1_FLAGに1をセットする
end else begin
chat_cnt <= chat_cnt + 1 ;
chat_cnt_flag <= 1'b0 ;
end
end
always@(posedge hclk)
begin
if(chat_cnt_flag == 1'b1 )begin
chat_cnt_toggle_flag <= !chat_cnt_toggle_flag ;
end
end
assign CLED_out = chat_cnt_toggle_flag ;
/************************************************************************/
// always@(negedge rd_clk1 or negedge RST)begin
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt1 <= 32'h00000000 ;
// end else if(swchatcnt1 == swchatcntof)begin
end else if(swchatcnt1 == swchantcntofsw1)begin
swchatcnt1 <= 32'h00000000 ;
swchat1_flag<= 1'b1;
end else begin
swchatcnt1 <= swchatcnt1 + 1 ;
swchat1_flag<=1'b0;
end
end
always@(posedge hclk)
begin
if(swchatcnt1 == 1'b1 )begin
swchat1_toggle<= !swchat1_toggle;
end
end
always@(posedge hclk)begin
//always@(posedge hclk )begin
// always@(negedge chat_cnt_toggle_flag)begin
if(swchatcnt1 == 32'h00000000 ) begin
// swchatbuf1 <= SW1;
// sw1 <= ~swchatbuf1 && ~SW1;
sw1 <= ~SW1; //20/01/27
end else
sw1 <= 1'b0;
end
assign SW1OUT = sw1;
/************************************************************************/
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt2 <= 32'h00000000 ;
// end else if(swchatcnt1 == swchatcntof)begin
end else if(swchatcnt2 == swchantcntofsw2)begin
// end else if(swchatcnt2 == swchatcntof)begin // 10/15
swchatcnt2 <= 32'h00000000 ;
end else begin
swchatcnt2 <= swchatcnt2 + 1 ;
end
end
always@(posedge hclk )begin
// always@(negedge chat_cnt_toggle_flag)begin
if(swchatcnt2 == 32'h00000000 ) begin
// swchatbuf2 <= SW2;
// sw2 <= ~swchatbuf2 && ~SW2;
sw2 <= ~SW2; //2001/27
end else
sw2 <= 1'b0;
end
/************************************************************************/
//always@(posedge hclk or negedge RST)begin //12/28
always@(posedge rd_clk1 or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt3 <= 32'h00000000 ;
// end else if(swchatcnt3 == swchantcntofsw1)begin
//9/30
end else if(swchatcnt3 == swchantcntofsw3)begin
swchatcnt3 <= 32'h00000000 ;
end else begin
swchatcnt3 <= swchatcnt3 + 1 ;
end
end
/*
//always@(posedge SW3 or posedge rd_clk1)begin//12/28
always@(posedge rd_clk1)begin//12/28
// always@(posedge rd_clk1)begin
// always@(negedge chat_cnt_toggle_flag)begin
if(rd_clk1 ) begin
swchatbuf3 <= SW3;
sw3 <= ~swchatbuf3;
// sw3 <= ~SW3;
end else
swchatbuf3<=1'b1;
sw3 <= 1'b0;
end
*/
//always@(posedge SW3 or posedge rd_clk1)begin//12/28
always@(posedge rd_clk1)begin//12/28
// always@(posedge rd_clk1)begin
// always@(negedge chat_cnt_toggle_flag)begin
if(swchatcnt3==32'h00000000 ) begin
// swchatbuf3 <= SW3;
// sw3 <= ~swchatbuf3 && ~SW3; //20/1/27
sw3 <= ~SW3;
end else
//swchatbuf3<=1'b1;
sw3 <= 1'b0;
end
assign SW3OUT =sw3;
/************************************************************************/
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt4 <= 32'h00000000 ;
end else if(swchatcnt4 == swchatcntof)begin
swchatcnt4 <= 32'h00000000 ;
end else begin
swchatcnt4 <= swchatcnt4 + 1 ;
end
end
always@(posedge hclk )begin
//always@(posedge rd_clk1 )begin
if(swchatcnt4 == 32'h00000000 ) begin
// swchatbuf4 <= SW4;
// sw4 <= ~swchatbuf4 && ~SW4;
sw4<= ~SW4 ;
end else
sw4 <= 1'b0;
end
/************************************************************************/
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt5 <= 32'h00000000 ;
end else if(swchatcnt5 == swchatcntof)begin
swchatcnt5 <= 32'h00000000 ;
end else begin
swchatcnt5 <= swchatcnt5 + 1 ;
end
end
always@(posedge hclk )begin
if(swchatcnt5 == 32'h00000000 ) begin
// swchatbuf5 <= SW5;
// sw5 <= ~swchatbuf5 && ~SW5;
sw5<=~SW5;
end else
sw5 <= 1'b0;
end
/************************************************************************/
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
//always@(cur or sw1 or sw2 or sw3)begin
always@( posedge cur[0] or posedge cur[1] or posedge cur[2] or posedge cur[3] or posedge sw1 or posedge sw2 )begin
case(cur)
NORMAL:if(sw1) //3'b000
nxt <= READID ;
else
nxt <= NORMAL;
READID:if(sw1) //3'b001
nxt <= NORMAL ;
else if(sw2)
nxt <= READSTATUS;
else
nxt <= READID;
READSTATUS:if(sw1) //3'b010
nxt <= NORMAL ;
else if(sw2)
nxt <= READPAGE;
else
nxt <= READSTATUS;
READPAGE:if(sw1) //3'b011
nxt <= NORMAL ;
else if(sw2)
nxt <= ERASEBLOCK;
else
nxt <= READPAGE ;
ERASEBLOCK:if(sw1) //
nxt <= NORMAL ;
else if(sw2)
nxt <= PROGRAMPAGE;
else
nxt <= ERASEBLOCK ;
PROGRAMPAGE:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= READPARAMPAGE;
else
nxt <= PROGRAMPAGE ;
READPARAMPAGE:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= READUNIID;
else
nxt <= READPARAMPAGE ;
READUNIID:if(sw1)
nxt <= NORMAL ;
else if(sw2)
// nxt <= READID;
nxt <=COMPARECHECK;
else
//parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,
//READUNIID=4'b0111,COMPARECHECK=4'b1000,AdSel Start=4'b1001,AdSel End 4'b1010 ,Adcycl =4'b1011,Data Input=4'b1100,Load=4'b1101,;
nxt <= READUNIID ;
COMPARECHECK:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= AdSelStart;
else
nxt <= COMPARECHECK ;
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
AdSelStart:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= AdSelEnd;
else
nxt <= AdSelStart ;
AdSelEnd:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= Adcycl;
else
nxt <= AdSelEnd ;
Adcycl:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= DataInput;
else
nxt <= Adcycl ;
DataInput:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= Load;
else
nxt <= DataInput ;
Load:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= ErsPrgCom;
else
nxt <= Load ;
ErsPrgCom:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= READID;
else
nxt <= ErsPrgCom ;
default:nxt <=4'b0000;
endcase
end
assign STATUSLEDOUT[3:0] = ~cur[3:0] ;
//assign DATA = (cle ||ale||~wen)?tsw:8'hzz; //10/10動作している11/30
assign DATA = (cle ||ale||wenspan)?tsw:8'hzz; //10/10動作している
//assign DATA = (cle ||ale||wenspan)?dataout:8'hzz; //12/28実験
//assign DATA = (cle ||ale)?tsw:8'hzz;// 10/22~11/22まではこれで動作している
always@(posedge ren)
begin
//if(rd_clk1)
din <= DATA ;
end
//always@(posedge wenspan or posedge cle posedge ale)
/*always@(wen)
if(cle ==1'b1||ale ==1'b1||wenspan==1'b1)begin
//if(rd_clk1)
dataout <= tsw ;
end else begin
dataout <=8'hzz;
end
*/
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
//always@(posedge SW3 or negedge RST)
always@(posedge sw3 or negedge RST)
begin
if(RST == 1'b0 ) begin
addrs4 <= 8'h00 ;
addre4<=8'h00;
end else if(cur[3:0] ==4'b1001 )begin
if(SW5==1'b0)begin
addrs4 <= addrs4 - 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end else begin
addrs4 <= addrs4 + 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end
end else if(cur[3:0] ==4'b1010 )begin
if(SW5==1'b0)begin
addre4 <= addre4 - 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end else begin
addre4 <= addre4 + 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end
end else if(cur[3:0] ==4'b1100)begin
if(SW5==1'b0)begin
wdatain[7:4]<= wdatain[7:4] -1;
end else begin
wdatain[7:4]<= wdatain[7:4] +1;
end
end
end
//always@(posedge SW4 or negedge RST)
always@(posedge sw4 or negedge RST)
begin
if(RST == 1'b0 ) begin
addrs3 <= 8'h00 ;
addre3<= 8'h00;
// erdata <= ram[0];
loadcnt <= 8'b00000000;
end else if(cur[3:0] ==4'b1001 )begin //AdSelStart
if(SW5==1'b0)begin
addrs3 <= addrs3 - 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end else begin
addrs3 <= addrs3 + 1;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end
end else if(cur[3:0] ==4'b1010 )begin //AdSelEnd
if(SW5==1'b0)begin
addre3 <= addre3 - 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end else begin
addre3 <= addre3 + 1;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end
end else if(cur==4'b1100)begin
if(SW5==1'b0)begin
wdatain[3:0]<= wdatain[3:0] -1;
end else begin
wdatain[3:0]<= wdatain[3:0] +1;
end
end else if(cur==4'b1101)begin
if(SW5==1'b0)begin
// erdata <= ram[loadcnt];
loadcnt[7:0] <= loadcnt[7:0] -1;
end else begin
// erdata <= ram[loadcnt];
loadcnt[7:0] <= loadcnt[7:0] +1;
end
end
end
always@(posedge hclk)
begin
// ram[loadcnt]<=ewdata;
//end else begin
erdata <= ram[loadcnt];
erdatanxt <= ram[loadcnt+1];
loadcntnxt <= loadcnt+1;
end
//end
always @( posedge rd_clk1) begin
if ( RST==1 'b0 ) begin
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan<= 1'b0;
tsw <= 8 'h00;
adcyccnt <= 17'b00000000000000000;
// tsw <= 16 'h0000;
cntw <= 24 'h0000000;
next <= 10'd0;
r_cyc_count1<=16'h0000;
w_cyc_count1<=16'h0000;
e_cyc_count1 <=10'b0000000000;
instatus<=4'b0000;
bramstorecnt=16'h0000;
bramstorecntoffset=16'h0100;
bramstorecntoffset2=16'h0200;
bramstorecntoffset3=16'h0600;
storecnt =8'h00;
// c_cyc_count1<=16'h0000;
for(i=0;i<WORDS;i=i+1) ram[i]=0; // 11/20
end else if (cntw == 24 'h000064 )begin
cntw <= 24 'h0000;
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
end else if(sw3 ==1'b1 && cur[3:0] ==4'b0001 )begin //ReadID
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
next <=10'd1;
cntw <= 24 'h0000;
instatus <=4'b0000;
end else if(sw3 ==1'b1 && cur[3:0] == 4'b0010)begin //Read Status
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
next <=10'd30;
cntw <= 24'h0000;
instatus <=4'b0000;
end else if(sw3 ==1'b1 && cur[3:0] == 4'b0011)begin //read page
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
bramstorecnt=16'h0000;
next <=10'd40;
instatus <=4'b0000;
cntw <= 24'h0000;
//11/20
end else if(sw3 ==1'b1 && cur[3:0]== 4'b0100)begin //ERASE BLOCK
for(i=0;i<WORDS;i=i+1) ram[i]=0;
// e_cyc_count1 <=10'b0000000000;
e_cyc_count1 <=10'b0000000000;
bramstorecnt=16'h0000;
storecnt =8'h00;
bramstorecntoffset=16'h0100;
bramstorecntoffset2=16'h0200;
cntw <= 24'h0000;
instatus <=4'b0000;
next <= 10'd70;
end else if(sw3 ==1'b1 && cur[3:0]== 4'b0101)begin //PROGRAM PAGE
for(i=0;i<WORDS;i=i+1) ram[i]=0;
bramstorecnt=16'h0000;
storecnt =8'h00;
bramstorecntoffset=16'h0100;
bramstorecntoffset2=16'h0200;
// adcyccnt <= 16'h00;
instatus <=4'b0000;
cntw <= 24'h0000;
next <= 10'd100;
end else if(sw3 ==1'b1 && cur[3:0]== 4'b0110)begin //Readall c0
for(i=0;i<WORDS;i=i+1) ram[i]=0;
bramstorecnt=16'h0000;
storecnt =8'h00;
bramstorecntoffset=16'h0100;
bramstorecntoffset2=16'h0200;
adcyccnt <= 17'b00000000000000000;
// adcyccnt <= 16'h00;
instatus <=4'b0000;
cntw <= 24'h0000;
next <= 10'd190;
end else if(sw3 ==1'b1 && cur[3:0]== 4'b0111)begin //Readall C800
for(i=0;i<WORDS;i=i+1) ram[i]=0;
bramstorecnt=16'h0000;
storecnt =8'h00;
bramstorecntoffset=16'h0100;
bramstorecntoffset3=16'h0600;
adcyccnt <= 17'b00000000000000000;
// adcyccnt <= 16'h00;
instatus <=4'b0000;
cntw <= 24'h0000;
next <= 10'd300;
end else if(sw3 ==1'b1 && cur[3:0]== 4'b1000)begin //COMPARECHECK
for(i=0;i<WORDS;i=i+1) ram[i]=0;
bramstorecnt=16'h0000;
storecnt =8'h00;
bramstorecntoffset=16'h0100;
bramstorecntoffset2=16'h0200;
instatus <=4'b0000;
cntw <= 24'h0000;
next <= 10'd140;
end else if(sw3 ==1'b1 && cur[3:0]== 4'b1110)begin //ErsRePrgCom
for(i=0;i<WORDS;i=i+1) ram[i]=0;
instatus <=4'b0000;
e_cyc_count1 <=10'b0000000000;
bramstorecnt=16'h0000;
storecnt =8'h00;
bramstorecntoffset=16'h0100;
bramstorecntoffset2=16'h0200;
cntw <= 24'h0000;
next <= 10'd70;//d70 erase d40 to read
end else begin
cntw <= cntw + 1'b1;
case (next)
10'd254 :if ( cntw == 24 'd2) begin //1/5/ d2
if(RB == 1'b0)begin
next <= 10'd254;
end else begin
if(cur[3:0]==4'b0011)begin //read page
// if(adcyccnt == adcyc )begin
if(adcyccnt > adcyc )begin // 12/15
toramen <=1'b0;
storecnt =8'h00;
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
adcyccnt <= 17'b00000000000000000;
r_cyc_count1 <= 16'h00;
instatus <=4'b0000; //3/8
next <= 10'd00;
// end else if(adcyccnt < adcyc)begin
end else if(adcyccnt < adcyc||adcyccnt == adcyc && instatus == 4'b1000 )begin
//read page
toramen <=1'b0;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
//tsw <= 8 'h0000;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt +1;
next <= 10'd40;
end
end else if(cur[3:0]==4'b0100)begin //eraseblock
if(e_cyc_count1 == ecyc )begin
toramen <=1'b0;
storecnt =8'h00;
bramstorecnt=16'h0000;
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
adcyccnt <= 17'b00000000000000000;
e_cyc_count1 <= 10'b0000000000;
next <= 10'd00;
end else if( e_cyc_count1<ecyc && instatus ==4'b0001)begin //ffbf dec 65471 65535-64
//read page
toramen <=1'b0;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
//tsw <= 8 'h0000;
cntw <= 24 'h000000;
e_cyc_count1 <= e_cyc_count1 + 1 ;
next <= 10'd70;
end
end else if(cur[3:0]==4'b0101)begin //program PAGE
// if(DATA == 8'he0 ||DATA == 8'hc0)begin
// if(adcyccnt == adcyc )begind
if(adcyccnt > adcyc )begin // 12/15
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
adcyccnt <= 17'b00000000000000000;
w_cyc_count1 <=16'h00;
next <= 10'd00;
// end else if(adcyccnt < adcyc)begin
end else if(adcyccnt < adcyc||adcyccnt == adcyc )begin
//read page
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
//tsw <= 8 'h0000;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt+1 ;
next <= 10'd100;
end
//end else begin
// next <= 10'd254;
// end
end else if(cur[3:0]==4'b0110)begin //readall c0 page
if(adcyccnt > adcyc )begin // 12/15
toramen <=1'b0;
storecnt =8'h00;
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
adcyccnt <= 17'b00000000000000000;
instatus <=4'b0000;
next <= 10'd00;
end else if(adcyccnt < adcyc||adcyccnt == adcyc && instatus ==4'b1111 )begin
toramen <=1'b0;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
next <= 10'd190;
end
end else if(cur[3:0]==4'b0111)begin //readall c800 page
if(adcyccnt > adcyc )begin // 12/15
toramen <=1'b0;
storecnt =8'h00;
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
instatus<=4'b0000;
cntw <= 24 'h000000;
adcyccnt <= 17'b00000000000000000;
next <= 10'd00;
end else if(adcyccnt < adcyc||adcyccnt == adcyc && instatus ==4'b0111)begin
toramen <=1'b0;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
next <= 10'd300;
end
end else if(cur[3:0]==4'b1000)begin //COMPARECHECK=4'b1000
// if(adcyccnt == adcyc )begin
if(adcyccnt > adcyc )begin // 12/15
/* if(din != wdatain)begin
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din[7:0]};
// storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
adcyccnt <= 16'h00;
// c_cyc_count1<=16'h00;
next <= 10'd00;
end else begin*/
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
adcyccnt <= 17'b00000000000000000;
// c_cyc_count1<=16'h00;
next <= 10'd00;
// end
// end else if(adcyccnt < adcyc)begin
end else if(adcyccnt < adcyc||adcyccnt == adcyc && instatus == 4'b0100 )begin
/* if(din != wdatain)begin
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din[7:0]};
// storecnt <= storecnt + 1;
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt +1;
// c_cyc_count1<=16'h00;
next <= 10'd140;
end else begin*/
//read page
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
//tsw <= 8 'h0000;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt +1;
next <= 10'd140;
// end
end
end
if(cur[3:0]==4'b1110)begin
if(instatus == 4'b1000)begin //4'b1000 read
if(adcyccnt > adcyc )begin // 12/15
for(i=0;i<WORDS;i=i+1) ram[i]=0;
bramstorecnt=16'h0000;
storecnt =8'h00;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
adcyccnt <= 17'b00000000000000000;
e_cyc_count1 <= 10'b0000000000;
w_cyc_count1<=16'h0000;
r_cyc_count1<=16'h0000;
// instatus <=4'b0000; //20200222 3/7
cntw <= 24 'h000000;
bramstorecntoffset=16'h0100;
next <= 10'd100; //d100 to prog //to erase
end else if(adcyccnt < adcyc||adcyccnt == adcyc && instatus == 4'b1000)begin
// bramstorecnt=16'h0000;
storecnt =8'h00;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
next <= 10'd40; //to Read Page
end
end else if(instatus == 4'b0001)begin //4'b0001 erase
if(e_cyc_count1 == ecyc )begin
// cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24'h000000;
adcyccnt <= 17'b00000000000000000;
e_cyc_count1 <= 10'b0000000000;
r_cyc_count1<=16'h0000;
bramstorecnt=16'h0000;
storecnt =8'h00;
next <= 10'd40; //to read
end else if( e_cyc_count1 < ecyc && instatus == 4'b0001)begin //ffbf dec 65471 65535-64
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24'h000000;
e_cyc_count1 <= e_cyc_count1 + 1 ;
// bramstorecnt=16'h0000;
// storecnt =8'h00;
next <= 10'd70; //to erase again
end
end else if(instatus == 4'b0010)begin //program
if(adcyccnt > adcyc )begin // 12/15
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24'h000000;
adcyccnt <= 17'b00000000000000000;
bramstorecnt=8'h00;
storecnt =8'h00;
w_cyc_count1<=16'h0000;
next <= 10'd140; //compare read
end else if(adcyccnt < adcyc||adcyccnt == adcyc && instatus == 4'b0010 )begin
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
cntw <= 24'h000000;
next <= 10'd100; //to program again
end
end else if(instatus == 4'b0100)begin //compare read
if(adcyccnt > adcyc )begin // 12/15
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
// w_cyc_count1<=16'h0000;
adcyccnt <= 17'b00000000000000000;
instatus <=4'b0000;
next <= 10'd190; //00 d190 readall
end else if(adcyccnt < adcyc||adcyccnt == adcyc && instatus == 4'b0100 )begin
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
next <= 10'd140;
end
end else if(instatus == 4'b1111)begin //Readall
if(adcyccnt > adcyc )begin // 12/15
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
// w_cyc_count1<=16'h0000;
adcyccnt <= 17'b00000000000000000;
instatus <=4'b0000;
next <= 10'd00;
end else if(adcyccnt < adcyc||adcyccnt == adcyc && instatus == 4'b1111 )begin
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
next <= 10'd190;
end
end
end
end
end
// 10'd0:if(cntw ==24'd2)begin
// instatus <=4'b0000;
// end
10'd1 : if ( cntw == 24 'd3) begin // cntw==247d0だと動作しない。
// 10'd1 : if ( cntw == 24 'd0) begin //
// 10'd1 : if ( rdid_clk1 ==1'b1) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b0;
tsw <= 8 'hzz;
//tsw <= 16 'hzzzz;
cntw <= 24 'h000000;
next <= 10'd2;
end
10'd2 : if ( cntw == 24 'd2 ) begin //d1
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hff;
// tsw <= 16 'h00ff;
cntw <= 24 'h000000;
next <= 10'd3;
end
10'd3 : if ( cntw == 24 'd2 ) begin //1
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hff; //dataout ffh
// tsw <= 16 'h00ff;
cntw <= 24 'h000000;
next <= 10'd4;
end
10'd4 : if ( cntw == 24 'd4 ) begin //8
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hff;
// tsw <= 16 'h00ff;
cntw <= 24 'h000000;
next <= 10'd5;
end
10'd5 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
// tsw <= 16 'hzzzz;
cntw <= 24 'h000000;
next <= 10'd6;
end
/////////////////////////command end///////////////////////////
10'd6 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h90;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd7;
end
10'd7 : if ( cntw == 24 'd2 ) begin//d1
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h90;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd8;
end
10'd8 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h90;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd9;
end
10'd9 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd10;
end
10'd10 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd11;
end
10'd11 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd12;
end
10'd12 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd13;
end
10'd13 : if ( cntw == 24 'd21 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd14;
end
10'd14 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd15;
end
10'd15 : if ( cntw == 24 'd4 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;// read trigger initiarize
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd16;
end
10'd16 : if ( cntw == 24 'd4 ) begin //rs_enb
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 1Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd17;
end
10'd17 : if ( cntw == 24 'd4 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;// read trigger initiarize
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd18;
end
10'd18 : if ( cntw == 24 'd4 ) begin //rs_enb
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 1Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd19;
end
10'd19 : if ( cntw == 24 'd4 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;// read trigger initiarize
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd20;
end
10'd20 : if ( cntw == 24 'd4 ) begin //rs_enb
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 1Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd21;
end
10'd21 : if ( cntw == 24 'd4 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;// read trigger initiarize
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd22;
end
10'd22 : if ( cntw == 24 'd4 ) begin //rs_enb
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 1Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd23;
end
10'd23 : if ( cntw == 24 'd12 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b1;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd255;
end
10'd255 : if ( cntw == 24 'd1 ) begin/////////////////////////////////////////////////////////////////////////////////////////////////////10'd255
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
tsw <= 8 'hzz; //20/2/18 00
cntw <= 24 'h000000;
storecnt =8'h00;
// w_cyc_count1 <= 16'h0000; //11/3
// r_cyc_count1 <= 16'h0000; //11/3
// rdidframe<=1'b0;
next <= 10'd00;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
10'd30 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd31;
end
10'd31 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd32;
end
10'd32 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd33;
end
10'd33 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd34;
end
10'd34 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd35;
end
10'd35 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd36;
end
10'd36 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd37;
end
10'd37 : if ( cntw == 24 'd21 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd38;
end
10'd38 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd39;
end
10'd39 : if ( cntw == 24 'd2 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd255;
end
10'd40 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
instatus <= 4'b1000;
cntw <= 24 'h000000;
r_cyc_count1<=16'h0000;
next <= 10'd41;
end
10'd41 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd42;
end
10'd42 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd43;
end
10'd43 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd44;
end
10'd44 : if ( cntw == 24 'd6 ) begin //LSB
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw<=r_cyc_count1[7:0];
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 10'd45;
end
10'd45 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw<= r_cyc_count1[7:0];
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 10'd46;
end
10'd46 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd47;
end
10'd47 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= r_cyc_count1[15:8];
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 10'd48;
end
10'd48 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= r_cyc_count1[15:8];
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 10'd49;
end
10'd49 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd50;
end
10'd50 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs3+adcyccnt[7:0];
// tsw <= addrs3;
cntw <= 24 'h000000;
next <= 10'd51;
end
10'd51 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs3+adcyccnt[7:0];
// tsw <= addrs3;
cntw <= 24 'h000000;
next <= 10'd52;
end
10'd52 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd53;
end
10'd53 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
// tsw <= addrs4;
cntw <= 24 'h000000;
next <= 10'd54;
end
10'd54 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
// tsw <= addrs4;
cntw <= 24 'h000000;
next <= 10'd55;
end
10'd55 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd56;
end
10'd56 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd57;
end
10'd57 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd58;
end
10'd58 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd59;//11/23 12/28 d62
end
10'd59 : if ( cntw == 24 'd21 ) begin
if(RB == 1'b0)begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz; //3/3/0000
cntw <= 24 'h000000;
next <= 10'd58; //
end else begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz; //3/3/0000
cntw <= 24 'h000000;
// r_cyc_count1<=16'h0000;
// adcyccnt<=16'h0000;
next <= 10'd62;
end
end
10'd60 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'hzz; //3/3/0000
cntw <= 24 'h000000;
next <= 10'd61;
end
10'd61:if(cntw==24'd1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b0;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd61;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd62;
end
end
10'd62:if(cntw==24'd5)begin
// if(r_cyc_count1 < 16'h0003)begin
// if(r_cyc_count1 < caddrs1 )begin ///<=
// if(adcyccnt < adcyc +1)begin
if(r_cyc_count1 < caddrs1 || r_cyc_count1 == caddrs1)begin ///<=
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd66;//63
// end else if (r_cyc_count1 ==16'h0003)begin
// end else if (r_cyc_count1 == caddrs1)begin //+1
end else if (r_cyc_count1 > caddrs1 )begin //+1 //11/30==
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt +1;//11/24
// r_cyc_count1 <= 16'h0000;
//next <= 10'd254;//62
next <= 10'd63;
end
end
10'd63:if(cntw==24'd8)begin //3/2 d2
// if(RB == 1'b0)begin
// cntw <= 24 'h000000;
// next <= 10'd62;
// end else
if(din == 8'h00 && r_cyc_count1 == 16'h800)begin
// toramdata<={addrs4+e_cyc_count1[9:2],addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0],addrs2[3:0],addrs1,din[7:0]};
toramen<=1'b0;
toramdata<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+r_cyc_count1[11:8],addrs1+r_cyc_count1[7:0],din[7:0]};
//adcyccnt <= adcyccnt + 64;
cntw <= 24 'h000000;
next <= 10'd64;//62
end else begin
adcyccnt <= adcyccnt +1;//11/24 2/4
r_cyc_count1 <= 16'h0000;
cntw <= 24 'h000000;
next <= 10'd254;//62
end
end
10'd64:if(cntw==24'd2)begin
toramen <=1'b1;
// adcyccnt <= adcyccnt + 64;
cntw <= 24 'h000000;
next <= 10'd65;//62
end
10'd65:if(cntw==24'd2)begin
toramen <=1'b0;
bramstorecnt<=bramstorecnt+1;
adcyccnt <= adcyccnt + 64;
// storecnt<=storecnt+1;
cntw <= 24 'h000000;
next <= 10'd254;//62
end
10'd66:if(cntw==24'd4)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd67;
end
10'd67:if(cntw==24'd1) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
r_cyc_count1 <=r_cyc_count1 +1;
next <= 10'd61; //62 11/19
end
10'd70 : if ( cntw == 24 'd3 ) begin //
toramren <=1'b0;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
instatus<= 4'b0001;
//adcyccnt<=16'h0000;
//e_cyc_count1<=10'b0000000000;
cntw <= 24 'h000000;
next <= 10'd71;
end
10'd71 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd72;
end
10'd72 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b0;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd73;
end
10'd73 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd74;
end
10'd74:if( cntw ==24'd2)begin //2020222 d2
//if(RB == 1'b0)begin
//cntw <= 24 'h000000;
//next <= 10'd73;
//end else if(bramstorecnt < 16'd99 || bramstorecnt == 16'd99)begin
if(bramstorecnt < 16'd99 || bramstorecnt == 16'd99)begin
// if(fromramdata[35:20] == {addrs4+e_cyc_count1[9:2],addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0]})begin
if(fromramdata[35:26] == {addrs4+e_cyc_count1[9:2],addrs3[7:6]+e_cyc_count1[1:0] } && fromramdata[35:26] != 10'b0000000000)begin
// toramren <=1'b0;
// e_cyc_count1 <= e_cyc_count1 +1; //2020/2/22
// bramstorecnt <= bramstorecnt +1;
toramren <=1'b0;
cntw <= 24 'h000000;
next <= 10'd87;//87 2/29
end else begin
toramren <=1'b0;
// storecnt <= storecnt +1 ;
cntw <= 24 'h000000;
next <= 10'd75;
end
end else begin
toramren <=1'b0;
bramstorecnt <= 16'h0000;
//storecnt <= 10'd00;
cntw <= 24'h000000;
next <= 10'd75;
end
end
10'd75 : if ( cntw == 24 'd2 ) begin //2020/2/21 d1
toramren <=1'b0;
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h60;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd76;
end
10'd76 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h60;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd77;
end
10'd77 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd78;
end
10'd78 : if ( cntw == 24 'd6 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000 + e_cyc_count1[1:0];
tsw<= {addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0]};
// tsw <= addrs3;
cntw <= 24 'h000000;
next <= 10'd79;
end
10'd79 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000 + e_cyc_count1[1:0];
tsw<= {addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0]};
// tsw <= addrs3;
cntw <= 24 'h000000;
next <= 10'd80;
end
10'd80 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd81;
end
10'd81 : if ( cntw == 24 'd6 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000 + e_cyc_count1[9:2];
tsw<=addrs4+e_cyc_count1[9:2];
// tsw <= addrs4;
cntw <= 24 'h000000;
next <= 10'd82;
end
10'd82 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000 + e_cyc_count1[9:2];
tsw<=addrs4+e_cyc_count1[9:2];
// tsw <= addrs4;
cntw <= 24 'h000000;
next <= 10'd83;
end
10'd83 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd84;
end
10'd84 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hd0; //ERASE BLOCK command2 D0h
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd85;
end
10'd85 : if ( cntw == 24 'd2 ) begin //2/27 d1
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hd0; //ERASE BLOCK command2 D0h
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd86;
end
10'd86 : if ( cntw == 24 'd4 ) begin //2/27 d4
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hd0;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd87;
end
10'd87 : if ( cntw == 24 'd71 ) begin //d21 12/15 d42 2020/3/1
if(RB == 1'b0)begin
cle <= 1'b0; //2020/02/22 1'b1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next<= 10'd86;
end else begin
bramstorecnt <= bramstorecnt +1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd88;
end
end
10'd88 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd89;
end
10'd89 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd90;
end
10'd90 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd91;
end
10'd91 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'hzz;//1210
tsw <= 8'h0000;
cntw <= 24 'h000000;
next <= 10'd92;
end
10'd92 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd93;
end
10'd93 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd94;
end
10'd94 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd95;
end
10'd95 : if ( cntw == 24 'd72 ) begin //21//1/27 d70 2/22 d100 は動かない
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd96;
end
10'd96 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
bramstorecnttemp<= bramstorecnt;
bramstorecnt <= bramstorecntoffset ;
cntw <= 24 'h000000;
next <= 10'd97;//254 12/10
end
10'd97:if(cntw ==24'd2)begin //12/10
// if(din[0] == 1'b1 && bramstorecnt == 8'b00000000)begin
// bramstorecntoffset <= 8'b00010000;
//end else
if(din[0] ==1'b1)begin
//bramstorecnt <= bramstorecntoffset ;
//bramstorecntoffset <= bramstorecntoffset + 32;
toramen <=1'b0;
// errstatus<=din;
toramdata<={addrs4+e_cyc_count1[9:2],addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0],addrs2[3:0],addrs1,din[7:0]};//8,2,6,4,8,8
// storecnt <= storecnt + 1;
cntw <= 24'h000000;
next <= 10'd98;
end else if(din ==8'he0)begin
// errstatus<=din;
// toramdata<={addrs4+e_cyc_count1[9:2],addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0],addrs2[3:0],addrs1,din[7:0]};
// storecnt <= storecnt + 1;
// toramen<=1'b1;
toramen <=1'b0;
cntw <= 24'h000000;
// e_cyc_count1 <= e_cyc_count1;
bramstorecnt <= bramstorecnttemp;
// e_cyc_count1 <= e_cyc_count1 + 1 ;
next <= 10'd254;
end else begin
// toramdata<={addrs4+e_cyc_count1[9:2],addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0],addrs2[3:0],addrs1,din[7:0]};
// e_cyc_count1 <= e_cyc_count1;
bramstorecnt <= bramstorecnttemp;
toramen <=1'b0;
cntw <= 24'h000000;
// e_cyc_count1 <= e_cyc_count1 + 1 ;
next <= 10'd254;//252
end
end
10'd98:if(cntw==24'd2)begin
toramen <=1'b1;
// e_cyc_count1 <= e_cyc_count1;
cntw <= 24'h000000;
next <= 10'd99;
end
10'd99:if(cntw==24'd2)begin
bramstorecntoffset <= bramstorecntoffset +1 ;
bramstorecnt <= bramstorecnttemp;
// bramstorecnt<=8'b0;
toramen <=1'b0;
cntw <= 24'h000000;
// e_cyc_count1 <= e_cyc_count1 + 1 ;
next <= 10'd254;
end
// end
//////////////////////////////////ERASE BLOCK end///////////////////////////////////
////////////////////////////////////////////////////
//////////////////////////////PROGRAM PAGE START ////////////////0x05//////////////////////////////////////////////////////////////////////////////////////////program
10'd100 : if ( cntw == 24 'd3 ) begin ////d30 b12/10
toramren <=1'b0;
cle <= 1'b0;//1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
instatus<=4'b0010;
w_cyc_count1<=16'h0000;
// c_cyc_count1<=16'h0000;
cntw <= 24 'h000000;
next <= 10'd101;
end
10'd101 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b1;
cle <= 1'b0;//1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd102;
end
10'd102 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b0;
cle <= 1'b0;//1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd249;
end
10'd249 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b1;
cle <= 1'b0;//1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd250;
end
10'd250 : if ( cntw == 24 'd1 ) begin //
if(RB==1'b0)begin
cntw <= 24'h00000;
next <= 10'd249;
end else if(bramstorecnt < 16'd99||bramstorecnt==16'd99)begin
if(fromramdata[35:26] == {addrs4+adcyccnt[15:8],addrs3[7:6]+adcyccnt[7:6]} && fromramdata[35:26] != 10'b0000000000)begin
bramstorecnt <= bramstorecnt +1;
adcyccnt <= adcyccnt +1;
w_cyc_count1 <= 16'h0000;
toramren <=1'b0;
cntw <=24'h00000;
tsw <= 8 'hzz;
next <= 10'd130; // to read status
end else begin
bramstorecnt <= bramstorecnt +1; //20200222
toramren <=1'b0;
cntw <=24'h00000;
next <= 10'd103;
tsw <= 8 'hzz;
end
end else begin
cntw <=24'h00000;
toramren <=1'b0;
bramstorecnt <=16'h0000;
tsw <= 8 'hzz;
next <= 10'd103;
end
end
10'd103 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h80;
cntw <= 24 'h000000;
next <= 10'd104;
end
10'd104 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h80;
cntw <= 24 'h000000;
next <= 10'd105;
end
10'd105 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd106;
end
10'd106 : if ( cntw == 24 'd6 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs1;//+w_cyc_count1[7:0];
cntw <= 24 'h000000;
next <= 10'd107;
end
10'd107 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs1;//+w_cyc_count1[7:0];
cntw <= 24 'h000000;
next <= 10'd108;
end
10'd108 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd109;
end
10'd109 : if ( cntw == 24 'd4 ) begin //6//12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs2;//+w_cyc_count1[15:8];
cntw <= 24 'h000000;
next <= 10'd110;
end
10'd110 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs2;//+w_cyc_count1[15:8];
cntw <= 24 'h000000;
next <= 10'd111;
end
10'd111 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd112;
end
10'd112 : if ( cntw == 24 'd4 ) begin //6//12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 10'd113;
end
10'd113 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 10'd114;
end
10'd114 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd115;
end
10'd115 : if ( cntw == 24 'd4 ) begin //6//12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 10'd116;
end
10'd116 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 10'd117;
end
10'd117 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
// tsw <= wdatain; //12/28
cntw <= 24 'h000000;
next <= 10'd118; //116//119 //12/9変更
end
//////////////////////////////////////////
10'd118 : if ( cntw == 24 'd4 ) begin //d26 12/15 //12/9 d35で動作 計算上の限界はale lowからd28 ここはd26 d35 12/28 03ならd26でもOK 12/30 02 d4でNG
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
cntw <= 24 'h000000;
next <= 10'd117;//115
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;// 12/9 1'b0//12/28
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw<=8 'hzz; //wdatain から変更/12/28hzz->wdatain
// tsw<=wdatain;
cntw <= 24 'h000000;
next <= 10'd121; //119 //12/9 d117から変更
end
end
10'd119 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'haa;
// tsw<= w_cyc_count1[7:0];
// tsw<= w_cyc_count1[15:0];
tsw<=wdatain;
cntw <= 24 'h000000;
next <= 10'd120;
end
10'd120:if(cntw==24'd2)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
wenspan <= 1'b0;
//tsw <= 8 'haa;
//tsw<= w_cyc_count1[7:0];
//tsw<= w_cyc_count1[15:0];
tsw<=wdatain;
cntw <= 24 'h000000;
next <= 10'd121;
end
// 10'd119 : if ( cntw == 24 'd2 ) begin
// 10'd119 : if ( cntw == 24 'd35 ) begin//25 計算上の限界はale lowからd28 ここはd26 ｄ１１６で待たせるようにしたからd4で良い
10'd121 : if ( cntw == 24 'd16 )begin //d4 //12/11 1/2 01 ならd40でOK d16 3/10
// if(w_cyc_count1 < 16'h0003)begin
// if(adcyccnt < adcyc +1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b0;
tsw<=8'hzz;
cntw <= 24 'h000000;
next <= 10'd118; //2020/222
end else
if(w_cyc_count1 < caddrs1 || w_cyc_count1 == caddrs1 )begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;//122/8 1
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b1;
tsw<=wdatain;
// tsw<= w_cyc_count1[7:0];
cntw <= 24 'h000000;
next <= 10'd124;
end else if (w_cyc_count1 > caddrs1)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b1;
tsw <= wdatain;
cntw <= 24 'h000000;
adcyccnt <= adcyccnt +1;//11/24
next <= 10'd126;
end
end
10'd124 : if ( cntw == 24 'd4 ) begin //d4 12/11 12/12 d4 12/28
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
wenspan <= 1'b1;
tsw <= wdatain; //12/12
// tsw<= w_cyc_count1[7:0];
// tsw <= 16 'hzzzz; //12/01
cntw <= 24 'h000000;
next <= 10'd125;
end
10'd125:if(cntw==24'd2)begin //d2 12/11
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b0;
tsw<=8'hzz;
cntw <= 24 'h000000;
next <= 10'd124;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
wenspan <= 1'b0;
tsw <= 8 'hzz;
// tsw <= 16 'hzzzz;
cntw <= 24 'h000000;
w_cyc_count1 <= w_cyc_count1 +1;
next <= 10'd121; //119
end
end
10'd126 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h15;//12/28 10h
wenspan <= 1'b0;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd127;
end
10'd127 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h15;//12/28 10h
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd128;
end
10'd128 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h15;//12/28 10h
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd129;
end
10'd129 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd130;
end
10'd130 : if ( cntw == 24 'd3 ) begin // 2020/2/22 3
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;//12/28
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd131;
end
10'd131 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd132;
end
10'd132 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd133;
end
10'd133 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'hzz;//1210
tsw <= 8'h0000;
cntw <= 24 'h000000;
next <= 10'd134;
end
10'd134 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd135;
end
10'd135 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd136;
end
10'd136 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd137;
end
10'd137 : if ( cntw == 24 'd4 ) begin //1/3 d21
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd138;
end
10'd138 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd139;//254 12/10
end
10'd139:if(cntw ==24'd2)begin //12/10 d2/12/15 d21 12/24
if(din ==8'h80||din==8'hc0)begin
next <= 10'd137;
end else if(din ==8'he0)begin
next <= 10'd254;
end else begin
next <= 10'd137;
// end else begin //12/17
// next <=10'd254; //12/17
end
end
10'd140 : if ( cntw == 24 'd3 ) begin ////d30 b12/10
toramren <=1'b0;
cle <= 1'b0;//1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
instatus<=4'b0100;
w_cyc_count1<=16'h0000;
// c_cyc_count1<=16'h0000;
cntw <= 24 'h000000;
next <= 10'd141;
end
10'd141 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b1;
cle <= 1'b0;//1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd142;
end
10'd142 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b0;
cle <= 1'b0;//1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd143;
end
10'd143 : if ( cntw == 24 'd1 ) begin //
toramren <=1'b1;
cle <= 1'b0;//1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd144;
end
10'd144 : if ( cntw == 24 'd3 ) begin //
if(RB==1'b0)begin
cntw <= 24'h00000;
next <= 10'd143; //249
end else if(bramstorecnt < 16'd99||bramstorecnt==16'd99)begin
if(fromramdata[35:26] == {addrs4+adcyccnt[15:8],addrs3[7:6]+adcyccnt[7:6]} && fromramdata != 10'b0000000000)begin
bramstorecnt <= bramstorecnt +1;
adcyccnt <= adcyccnt +64;//1
w_cyc_count1 <= 16'h0000;
toramren <=1'b0;
cntw <=24'h00000;
tsw <= 8 'hzz;
next <= 10'd170; // to read status
end else begin
toramren <=1'b0;
cntw <=24'h00000;
tsw <= 8 'hzz;
next <= 10'd145;
end
end else begin
toramren <=1'b0;
bramstorecnt <=16'h0000;
cle <= 1'b1;
tsw <= 8 'hzz;
cntw <=24'h00000;
next <= 10'd145;
end
end
// toramren <= 1'b0;
// cle <= 1'b1;
// cen <= 1'b0;
// wen <= 1'b1;
// ale <= 1'b0;
// ren <= 1'b1;
// wp <= 1'b1;
// tsw <= 8 'h00;
// instatus<=4'b0100;
// w_cyc_count1<=16'h0000;
// c_cyc_count1<=16'h0000;
// tsw <= 8 'h5f; //movement check
// cntw <= 24 'h000000;
// next <= 10'd145;
// end
10'd145 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd146;
end
10'd146 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd147;
end
10'd147 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd148;
end
10'd148 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 10'd149;
end
10'd149 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 10'd150;
end
10'd150 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd151;
end
10'd151 : if ( cntw == 24 'd6 ) begin //disp_clear //6/12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 10'd152;
end
10'd152 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 10'd153;
end
10'd153 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd154;
end
10'd154 : if ( cntw == 24 'd6 ) begin //disp_clear //6/12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
// tsw <= 8 'h0001;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 10'd155;
end
10'd155 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
// tsw <= 8 'h0001;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 10'd156;
end
10'd156 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd157;
end
10'd157 : if ( cntw == 24 'd6 ) begin //disp_clear //6/12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 10'd158;
end
10'd158 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 10'd159;
end
10'd159 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd160;
end
10'd160 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd161;
end
10'd161 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd162;
end
10'd162 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
// c_cyc_count1<=16'h0000;
// storecnt<=8'b00000000;
//next <= 10'd159;
next <= 10'd163;//162 12/10 159 12/26
end
10'd163 : if ( cntw == 24 'd21 ) begin//12/14 70 12/26 70 12/30
if(RB == 1'b0)begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
cntw <= 24 'h000000;
next<= 10'd162;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0; //0 12/10
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
// c_cyc_count1<=16'h0000;
// storecnt<=8'b00000000;
next <= 10'd166; //160
end
end
10'd164 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd165;
end
10'd165:if(cntw==24'd1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b0;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd161;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd166;
end
end
10'd166:if(cntw==24'd5)begin //2019/11/17 'd5 d4 12/15 d5 12/24 d4だと05hでNG
// if(r_cyc_count1 < 16'h0003)begin
// if( c_cyc_count1 < caddrs1 || c_cyc_count1 == caddrs1)begin ///<=1
if( w_cyc_count1 < caddrs1 || w_cyc_count1 == caddrs1)begin ///<=1
// if(din != wdatain)begin
//////////////////////////////////
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din[7:0]};
// storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;//d0 12/12 12/15
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd167;
// end else if (c_cyc_count1 > caddrs1)begin //+1
end else if (w_cyc_count1 > caddrs1)begin //+1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//1//11/28
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
adcyccnt <= adcyccnt +1;
next <= 10'd170;//d166 //d254 12/26 165
end
// end else begin
/* cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd163;
// end else if (r_cyc_count1 ==16'h0003)begin
end
end*/
end
10'd167:if(cntw==24'd4)begin //d1 12/15
// if(din != wdatain)begin
// CCERR <= 1'b0;
// ram[storecnt]<={addrp4,addrp3,addrp2[3:0],addrp1,din};
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din};
// storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd168;
/* end else begin
CCERR <= 1'b1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd164;
end*/
end
10'd168:if(cntw==24'd4) begin //12/14 d2 12/14 d4 d4 12/26
if(din != wdatain )begin
// if(din != c_cyc_count1[7:0] )begin
// if(din != w_cyc_count1[7:0] )begin
// if(DATA != wdatain)begin
// CCERR <= 1'b0;
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din[7:0]};
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
// c_cyc_count1 <=c_cyc_count1 +1; //12/26
next <= 10'd169; //161 12/26 //162
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
// c_cyc_count1 <=c_cyc_count1 +1; //12/26
next <= 10'd169; //161 12/26 //162
end
end
10'd169 : if ( cntw == 24 'd1 ) begin //
// c_cyc_count1 <=c_cyc_count1 +1;
w_cyc_count1 <=w_cyc_count1 +1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd165; //161 2020222
end
///////////////////////////////////////////conparecheck
////////////////////////compare check read status compare check concluding////////////////////////////////////////////////////////////////////////////
10'd170 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd171;
end
10'd171 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd172;
end
10'd172 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 10'd173;
end
10'd173 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'hzz;//1210
tsw <= 8'h0000;
cntw <= 24 'h000000;
next <= 10'd174;
end
10'd174 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd175;
end
10'd175 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd176;
end
10'd176 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd177;
end
10'd177 : if ( cntw == 24 'd21 ) begin //21 12/16
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd178;
end
10'd178 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd179;//254 12/10
end
10'd179:if(cntw ==24'd2)begin //12/10
if(din ==8'h80||din==8'hc0)begin
next <= 10'd177; //d172 12/26
end else if(din ==8'he0)begin
next <= 10'd254;
end
end
///////////////////////////////////////////read page all start///0x03/////////////////////////////////////////////////////////////
10'd190 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
instatus <= 4'b1111;
cntw <= 24 'h000000;
r_cyc_count1<=16'h0000;
next <= 10'd191;
end
10'd191 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd192;
end
10'd192 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd193;
end
10'd193 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd194;
end
10'd194 : if ( cntw == 24 'd6 ) begin //LSB
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 10'd195;
end
10'd195 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 10'd196;
end
10'd196 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd197;
end
10'd197 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 10'd198;
end
10'd198 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 10'd199;
end
10'd199 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd200;
end
10'd200 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 10'd201;
end
10'd201 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 10'd202;
end
10'd202 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd203;
end
10'd203 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 10'd204;
end
10'd204 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 10'd205;
end
10'd205 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd206;
end
10'd206 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
cntw <= 24 'h000000;
next <= 10'd207;
end
10'd207 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
cntw <= 24 'h000000;
next <= 10'd208;
end
10'd208 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
cntw <= 24 'h000000;
next <= 10'd209;//11/23 12/28 d62
end
10'd209 : if ( cntw == 24 'd21 ) begin
if(RB == 1'b0)begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next<= 10'd208; //
end else begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd210;
end
end
/* 10'd200 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd201;
end
10'd201:if(cntw==24'd1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b0;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd201;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd202;
end
end */
10'd210:if(cntw==24'd5)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd211;
end
10'd211:if(cntw==24'd4)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
bramstorecnttemp2 <=bramstorecnt;//20
bramstorecnt <= bramstorecntoffset2;
cntw <= 24 'h000000;
next <= 10'd212;
end
10'd212:if(cntw==24'd2)begin
toramen<=1'b0;
toramdata<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+r_cyc_count1[11:8],addrs1+r_cyc_count1[7:0],din[7:0]};
cntw <= 24 'h000000;
next <= 10'd213;//62
end
10'd213:if(cntw==24'd2)begin
toramen <=1'b1;
adcyccnt <= adcyccnt + 64; //64/20/2/27
cntw <= 24 'h000000;
next <= 10'd214;//62
end
10'd214:if(cntw==24'd2)begin
bramstorecntoffset2 <= bramstorecntoffset2 +1 ;
bramstorecnt <= bramstorecnttemp2;
toramen <=1'b0;
bramstorecnt<=bramstorecnt+1;
cntw <= 24 'h000000;
next <= 10'd254;//62
end
10'd300 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
instatus <= 4'b0111;
cntw <= 24 'h000000;
r_cyc_count1<=16'h0000;
next <= 10'd301;
end
10'd301 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd302;
end
10'd302 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 10'd303;
end
10'd303 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd304;
end
10'd304 : if ( cntw == 24 'd6 ) begin //LSB
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 10'd305;
end
10'd305 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 10'd306;
end
10'd306 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd307;
end
10'd307 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 10'd308;
end
10'd308 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 10'd309;
end
10'd309 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd310;
end
10'd310 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 10'd311;
end
10'd311 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 10'd312;
end
10'd312 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd313;
end
10'd313 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 10'd314;
end
10'd314 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 10'd315;
end
10'd315 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd316;
end
10'd316 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
cntw <= 24 'h000000;
next <= 10'd317;
end
10'd317 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
cntw <= 24 'h000000;
next <= 10'd318;
end
10'd318 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
cntw <= 24 'h000000;
next <= 10'd319;//11/23 12/28 d62
end
10'd319 : if ( cntw == 24 'd21 ) begin
if(RB == 1'b0)begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next<= 10'd318; //
end else begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd320;
end
end
/* 10'd200 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd201;
end
10'd201:if(cntw==24'd1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b0;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd201;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd202;
end
end */
10'd320:if(cntw==24'd5)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd321;
end
10'd321:if(cntw==24'd4)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
bramstorecnttemp3 <=bramstorecnt;//20
bramstorecnt <= bramstorecntoffset3;
cntw <= 24 'h000000;
next <= 10'd322;
end
10'd322:if(cntw==24'd2)begin
toramen<=1'b0;
toramdata<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+r_cyc_count1[11:8],addrs1+r_cyc_count1[7:0],din[7:0]};
cntw <= 24 'h000000;
next <= 10'd323;//62
end
10'd323:if(cntw==24'd2)begin
toramen <=1'b1;
// adcyccnt <= adcyccnt + 64; //64/20/2/27 3/7
cntw <= 24 'h000000;
next <= 10'd324;//62
end
10'd324:if(cntw==24'd2)begin
// bramstorecntoffset3 <= bramstorecntoffset3 +1 ;
bramstorecnt <= bramstorecnttemp3;
toramen <=1'b0;
// bramstorecnt<=bramstorecnt+1;
cntw <= 24 'h000000;
next <= 10'd325;//62
end
/////////////////////random read 800h//////////////////////////////////////////
10'd325 : if ( cntw == 24 'd70 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h05;
// instatus <= 4'b0111;
cntw <= 24 'h000000;
r_cyc_count1<=16'h0000;
next <= 10'd326;
end
10'd326 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h05;
cntw <= 24 'h000000;
next <= 10'd327;
end
10'd327 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h05;
cntw <= 24 'h000000;
next <= 10'd328;
end
10'd328 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd329;
end
10'd329 : if ( cntw == 24 'd6 ) begin //LSB
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw<= 8'h00;
cntw <= 24 'h000000;
next <= 10'd330;
end
10'd330 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw<= 8'h00;
cntw <= 24 'h000000;
next <= 10'd331;
end
10'd331 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd332;
end
10'd332 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8'h08;
cntw <= 24 'h000000;
next <= 10'd333;
end
10'd333 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8'h08;
cntw <= 24 'h000000;
next <= 10'd334;
end
10'd334 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 10'd335;
end
//////////////////////////////rondom page read command2 E0h///////////////////////
10'd335 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'he0;
cntw <= 24 'h000000;
next <= 10'd336;
end
10'd336 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'he0;
cntw <= 24 'h000000;
next <= 10'd337;
end
10'd337 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'he0;
cntw <= 24 'h000000;
next <= 10'd338;//11/23 12/28 d62
end
//////////////////////////////////////////read cycle start//////read page///////////
10'd338 : if ( cntw == 24 'd21 ) begin
if(RB == 1'b0)begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next<= 10'd337; //
end else begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd339;
end
end
/* 10'd200 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd201;
end
10'd201:if(cntw==24'd1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b0;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd201;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd202;
end
end */
10'd339:if(cntw==24'd5)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 10'd340;
end
10'd340:if(cntw==24'd4)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
bramstorecnttemp3 <=bramstorecnt;//20
bramstorecnt <= bramstorecntoffset3;
cntw <= 24 'h000000;
next <= 10'd341;
end
10'd341:if(cntw==24'd2)begin
toramen<=1'b0;
toramdata[19:0]<={12'b100000000000,din[7:0]};
cntw <= 24 'h000000;
next <= 10'd342;//62
end
10'd342:if(cntw==24'd2)begin
toramen <=1'b1;
adcyccnt <= adcyccnt + 64; //64/20/2/27
cntw <= 24 'h000000;
next <= 10'd343;//62
end
10'd343:if(cntw==24'd2)begin
bramstorecntoffset3 <= bramstorecntoffset3 +1 ;
bramstorecnt <= bramstorecnttemp3;
toramen <=1'b0;
bramstorecnt<=bramstorecnt+1;
cntw <= 24 'h000000;
next <= 10'd254;//62
end
endcase
//end
end
end
//assign WP =wp;
assign WP =1'b1;
assign CLE = cle;
assign CE = cen;
assign WE = wen;
assign ALE =ale;
assign RE = ren;
//assign TSW=tsw;
//assign TSW = dataout;
assign R_CYC_COUNT1 = r_cyc_count1;
assign ADCYCCNT =adcyccnt;
assign EN = ~WE | ~RE ;
assign sEN = ~WE | ~RE;
assign W_CYC_COUNT1 =w_cyc_count1;
assign INSTATUS = instatus;
assign CCERR = ~RB;
endmodule
最新の20件
2024-04-08
2024-01-25
2024-01-24
2023-08-09
2023-07-14
2023-06-21
2023-04-22
2022-04-17
2022-02-13
2022-01-31
2021-12-17
2021-12-13
2021-10-27
2021-01-06
今日の20件
- counter: 168
- today: 1
- yesterday: 0
- online: 1
