verilog
1.nand_controller02_05
1-1.仕様(Specification)
1-2.タイミングチャート(timingchart)
1-3.回路図 circuit diagram
1-4-1.ピン一覧_全体
1-4-2.ピン一覧_Evaluation Bard
2.ソースコード(source code)
2.ソースコード上位層(source code upperlayer)
2.ソースコード下位層1(source code underlayer1)
2.ソースコード下位層2(source code underlayer2)
3.テストベンチソースコード(test bench source code)
4.タイミングコンストレインソースコード(constrain file)
5.結果(result)
1.nandc02_05beta †
目的：We will make the access Parallel NAND CONTROLLER to determine some bad blocks or etc...
1-1.仕様(Specification) †
(1)構成概略
主デバイス：Cyclone IV EP4CE22F17C6
Main Device:Cyclone IV EP4CE22F17C6
#ref(): File not found: "kousei1.png" at page "verilog/nand_controller"
(2)仕様
省略
Abbreviation
But, Target device which is assumed is MT29F1G08ABADA.
I may not assure any ohter devices.
1-2.タイミングチャート(timing chart) †
省略
Abbreviation
1-3.回路図(circuit diagram) †
省略
Abbreviation
1-4-1.Pin Assignment for All †
| To | Direction | Location | I/O Bank | VREF Group | Fitter Location | I/O Standard |
| ADDR[0] | Unknown | | | | | 3.3-V LVCMOS |
| ADDR[1] | Unknown | | | | | 3.3-V LVCMOS |
| ADDR[2] | Unknown | | | | | 3.3-V LVCMOS |
| ADDR[3] | Unknown | | | | | 3.3-V LVCMOS |
| ADDR[4] | Unknown | | | | | 3.3-V LVCMOS |
| ADDR[5] | Unknown | | | | | 3.3-V LVCMOS |
| ADDR[6] | Unknown | | | | | 3.3-V LVCMOS |
| store | Input | | | | PIN_R7 | 3.3-V LVCMOS |
| srw | Output | PIN_T11 | 4 | B4_N0 | PIN_T11 | 3.3-V LVCMOS |
| srs | Output | PIN_T10 | 4 | B4_N0 | PIN_T10 | 3.3-V LVCMOS |
| sen | Output | PIN_R12 | 4 | B4_N0 | PIN_R12 | 3.3-V LVCMOS |
| sdb[0] | Output | | | | PIN_G5 | 3.3-V LVCMOS |
| sdb[1] | Output | | | | PIN_C2 | 3.3-V LVCMOS |
| sdb[2] | Output | | | | PIN_N1 | 3.3-V LVCMOS |
| sdb[3] | Output | | | | PIN_K1 | 3.3-V LVCMOS |
| sdb[4] | Output | PIN_T12 | 4 | B4_N0 | PIN_T12 | 3.3-V LVCMOS |
| sdb[5] | Output | PIN_T13 | 4 | B4_N0 | PIN_T13 | 3.3-V LVCMOS |
| sdb[6] | Output | PIN_T15 | 4 | B4_N0 | PIN_T15 | 3.3-V LVCMOS |
| sdb[7] | Output | PIN_F13 | 6 | B6_N0 | PIN_F13 | 3.3-V LVCMOS |
| sSHIFT_CLK | Output | | | | PIN_P3 | 3.3-V LVCMOS |
| rw | Output | PIN_K15 | 5 | B5_N0 | PIN_K15 | 3.3-V LVCMOS |
| rs | Output | PIN_J13 | 5 | B5_N0 | PIN_J13 | 3.3-V LVCMOS |
| load | Input | | | | PIN_T2 | 3.3-V LVCMOS |
| en | Output | PIN_J16 | 5 | B5_N0 | PIN_J16 | 3.3-V LVCMOS |
| db[0] | Output | | | | PIN_E6 | 3.3-V LVCMOS |
| db[1] | Output | | | | PIN_K2 | 3.3-V LVCMOS |
| db[2] | Output | | | | PIN_P1 | 3.3-V LVCMOS |
| db[3] | Output | | | | PIN_T3 | 3.3-V LVCMOS |
| db[4] | Output | PIN_L13 | 5 | B5_N0 | PIN_L13 | 3.3-V LVCMOS |
| db[5] | Output | PIN_M10 | 4 | B4_N0 | PIN_M10 | 3.3-V LVCMOS |
| db[6] | Output | PIN_N14 | 5 | B5_N0 | PIN_N14 | 3.3-V LVCMOS |
| db[7] | Output | PIN_L14 | 5 | B5_N0 | PIN_L14 | 3.3-V LVCMOS |
| W_CYC_COUNT1[0] | Output | | | | PIN_F9 | |
| W_CYC_COUNT1[1] | Output | | | | PIN_D8 | |
| W_CYC_COUNT1[2] | Output | | | | PIN_E9 | |
| W_CYC_COUNT1[3] | Output | | | | PIN_C8 | |
| W_CYC_COUNT1[4] | Output | | | | PIN_L7 | |
| W_CYC_COUNT1[5] | Output | | | | PIN_B11 | |
| W_CYC_COUNT1[6] | Output | | | | PIN_M8 | |
| W_CYC_COUNT1[7] | Output | | | | PIN_A10 | |
| W_CYC_COUNT1[8] | Output | | | | PIN_F8 | |
| W_CYC_COUNT1[9] | Output | | | | PIN_J2 | |
| W_CYC_COUNT1[10] | Output | | | | PIN_P8 | |
| W_CYC_COUNT1[11] | Output | | | | PIN_L8 | |
| W_CYC_COUNT1[12] | Output | | | | PIN_J1 | |
| W_CYC_COUNT1[13] | Output | | | | PIN_T7 | |
| W_CYC_COUNT1[14] | Output | | | | PIN_B10 | |
| W_CYC_COUNT1[15] | Output | | | | PIN_N8 | |
| WP | Output | PIN_R14 | 4 | B4_N0 | PIN_R14 | 3.3-V LVCMOS |
| WE | Output | PIN_P9 | 4 | B4_N0 | PIN_P9 | 3.3-V LVCMOS |
| SW5 | Input | PIN_J14 | 5 | B5_N0 | PIN_J14 | 3.3-V LVCMOS |
| SW4 | Input | PIN_T9 | 4 | B4_N0 | PIN_T9 | 3.3-V LVCMOS |
| SW3OUT | Output | | | | PIN_F15 | 3.3-V LVCMOS |
| SW3 | Input | PIN_R9 | 4 | B4_N0 | PIN_R9 | 3.3-V LVCMOS |
| SW2 | Input | PIN_T14 | 4 | B4_N0 | PIN_T14 | 3.3-V LVCMOS |
| SW1OUT | Output | | | | PIN_B12 | 3.3-V LVCMOS |
| SW1 | Input | PIN_R13 | 4 | B4_N0 | PIN_R13 | 3.3-V LVCMOS |
| STATUSLEDOUT[0] | Output | PIN_E10 | 7 | B7_N0 | PIN_E10 | 3.3-V LVCMOS |
| STATUSLEDOUT[1] | Output | PIN_E11 | 7 | B7_N0 | PIN_E11 | 3.3-V LVCMOS |
| STATUSLEDOUT[2] | Output | PIN_D9 | 7 | B7_N0 | PIN_D9 | 3.3-V LVCMOS |
| STATUSLEDOUT[3] | Output | PIN_C9 | 7 | B7_N0 | PIN_C9 | 3.3-V LVCMOS |
| SHIFT_CLK | Output | | | | PIN_T6 | 3.3-V LVCMOS |
| SEVEN_SEG_DATA[0] | Output | PIN_D3 | 8 | B8_N0 | PIN_D3 | 3.3-V LVCMOS |
| SEVEN_SEG_DATA[1] | Output | PIN_C3 | 8 | B8_N0 | PIN_C3 | 3.3-V LVCMOS |
| SEVEN_SEG_DATA[2] | Output | PIN_A2 | 8 | B8_N0 | PIN_A2 | 3.3-V LVCMOS |
| SEVEN_SEG_DATA[3] | Output | PIN_A3 | 8 | B8_N0 | PIN_A3 | 3.3-V LVCMOS |
| SEVEN_SEG_DATA[4] | Output | PIN_B3 | 8 | B8_N0 | PIN_B3 | 3.3-V LVCMOS |
| SEVEN_SEG_DATA[5] | Output | PIN_B4 | 8 | B8_N0 | PIN_B4 | 3.3-V LVCMOS |
| SEVEN_SEG_DATA[6] | Output | PIN_A4 | 8 | B8_N0 | PIN_A4 | 3.3-V LVCMOS |
| SEVEN_SEG_DATA[7] | Output | PIN_B5 | 8 | B8_N0 | PIN_B5 | 3.3-V LVCMOS |
| SEL[1] | Output | PIN_B6 | 8 | B8_N0 | PIN_B6 | 3.3-V LVCMOS |
| SEL[2] | Output | PIN_A6 | 8 | B8_N0 | PIN_A6 | 3.3-V LVCMOS |
| SEL[3] | Output | PIN_A5 | 8 | B8_N0 | PIN_A5 | 3.3-V LVCMOS |
| SEL[4] | Output | PIN_D5 | 8 | B8_N0 | PIN_D5 | 3.3-V LVCMOS |
| SEL[5] | Output | PIN_A7 | 8 | B8_N0 | PIN_A7 | 3.3-V LVCMOS |
| SEL[6] | Output | PIN_C6 | 8 | B8_N0 | PIN_C6 | 3.3-V LVCMOS |
| SEL[7] | Output | PIN_B7 | 8 | B8_N0 | PIN_B7 | 3.3-V LVCMOS |
| SEL[8] | Output | PIN_D6 | 8 | B8_N0 | PIN_D6 | 3.3-V LVCMOS |
| SCK | Output | | | | PIN_E7 | 3.3-V LVCMOS |
| RST | Input | PIN_B8 | 8 | B8_N0 | PIN_B8 | 3.3-V LVCMOS |
| RE | Output | PIN_R11 | 4 | B4_N0 | PIN_R11 | 3.3-V LVCMOS |
| RB | Input | PIN_N16 | 5 | B5_N0 | PIN_N16 | 3.3-V LVCMOS |
| LOCKED_OUT | Output | | | | PIN_R3 | |
| LED_rdout | Output | | | | PIN_D11 | 3.3-V LVCMOS |
| LED_rdidout | Output | | | | PIN_N6 | 3.3-V LVCMOS |
| LED_out | Output | | | | PIN_P2 | 3.3-V LVCMOS |
| INSTATUS[0] | Output | PIN_A15 | 7 | B7_N0 | PIN_A15 | 3.3-V LVCMOS |
| INSTATUS[1] | Output | PIN_A13 | 7 | B7_N0 | PIN_A13 | 3.3-V LVCMOS |
| INSTATUS[2] | Output | PIN_B13 | 7 | B7_N0 | PIN_B13 | 3.3-V LVCMOS |
| INSTATUS[3] | Output | PIN_A11 | 7 | B7_N0 | PIN_A11 | 3.3-V LVCMOS |
| EN | Output | | | | PIN_C14 | 3.3-V LVCMOS |
| DATA[0] | Bidir | PIN_N9 | 4 | B4_N0 | PIN_N9 | 3.3-V LVCMOS |
| DATA[1] | Bidir | PIN_N11 | 4 | B4_N0 | PIN_N11 | 3.3-V LVCMOS |
| DATA[2] | Bidir | PIN_L16 | 5 | B5_N0 | PIN_L16 | 3.3-V LVCMOS |
| DATA[3] | Bidir | PIN_K16 | 5 | B5_N0 | PIN_K16 | 3.3-V LVCMOS |
| DATA[4] | Bidir | PIN_R16 | 5 | B5_N0 | PIN_R16 | 3.3-V LVCMOS |
| DATA[5] | Bidir | PIN_L15 | 5 | B5_N0 | PIN_L15 | 3.3-V LVCMOS |
| DATA[6] | Bidir | PIN_P15 | 5 | B5_N0 | PIN_P15 | 3.3-V LVCMOS |
| DATA[7] | Bidir | PIN_P16 | 5 | B5_N0 | PIN_P16 | 3.3-V LVCMOS |
| CLK | Input | PIN_R8 | 3 | B3_N0 | PIN_R8 | 3.3-V LVCMOS |
| CLED_out | Output | | | | PIN_N3 | 3.3-V LVCMOS |
| CLE | Output | PIN_R10 | 4 | B4_N0 | PIN_R10 | 3.3-V LVCMOS |
| CE | Output | PIN_P11 | 4 | B4_N0 | PIN_P11 | 3.3-V LVCMOS |
| CCERR | Output | | | | PIN_D1 | 3.3-V LVCMOS |
| ALE | Output | PIN_N12 | 4 | B4_N0 | PIN_N12 | 3.3-V LVCMOS |
| ADCYCCNT[0] | Output | | | | PIN_B14 | |
| ADCYCCNT[1] | Output | | | | PIN_D12 | |
| ADCYCCNT[2] | Output | | | | PIN_C11 | |
| ADCYCCNT[3] | Output | | | | PIN_A14 | |
| ADCYCCNT[4] | Output | | | | PIN_C15 | |
| ADCYCCNT[5] | Output | | | | PIN_D14 | |
| ADCYCCNT[6] | Output | | | | PIN_A12 | |
| ADCYCCNT[7] | Output | | | | PIN_D15 | |
| ADCYCCNT[8] | Output | | | | PIN_G16 | |
| ADCYCCNT[9] | Output | | | | PIN_G15 | |
| ADCYCCNT[10] | Output | | | | PIN_J15 | |
| ADCYCCNT[11] | Output | | | | PIN_N15 | |
| ADCYCCNT[12] | Output | | | | PIN_B16 | |
| ADCYCCNT[13] | Output | | | | PIN_F14 | |
| ADCYCCNT[14] | Output | | | | PIN_P14 | |
| ADCYCCNT[15] | Output | | | | PIN_C16 | |
| ADCYCCNT[16] | Output | | | | PIN_D16 | |
''1-4-2.Pin Assignment for Evaluation Bard "DE0-Nano" †
・Pin Assignment
省略
Abbreviation
2.ソースコード(source code) †
2-1.ソースコード(source code) Upperlayer †
module nandc04_02b(
CLK,
RST,
LED_out,
CLED_out,
SW1,
SW1OUT,
SW2,
SW3,
SW3OUT,
SW4,
SW5,
RB,
STATUSLEDOUT,
LED_rdout,
LED_rdidout,
CLE,
CE,
WE,
ALE,
RE,
// NEXTOUT,
WP,
// TSW,
W_CYC_COUNT1,
CCERR,
ADCYCCNT,
/************** using for7seg*module*/
DATA,
SEVEN_SEG_DATA,
SEL,
EN,
/******************LCD display***********/
SHIFT_CLK,
rw,
rs,
en,
db,
//LCD display
sSHIFT_CLK,
srw,
srs,
sen,
sdb,
//ram
load,
store,
// ADDR,
// ewdata,
// erdata,
SCK,
INSTATUS,
//clk
LOCKED_OUT
);
altpll1 U0(
.areset(RES_P),
.inclk0(CLK),
.c0(hclk),
.locked(hlocked)
);
/**********************/
input wire CLK ;
input wire RST;
input SW1,SW2,SW3,SW4,SW5;
input RB ;
output LED_out ;
output CLED_out;
output[3:0] STATUSLEDOUT;
output LED_rdout;
output LED_rdidout;
output CLE;
output CE;
output WE;
output ALE;
output RE;
output WP;
output SW1OUT;
output SW3OUT;
output EN;
//output[7:0] W_CYC_COUNT1;
output[16:0] ADCYCCNT;
output reg CCERR;
output wire[15:0] W_CYC_COUNT1;
/*7seg*/
output reg [7:0] SEVEN_SEG_DATA;
output[8:1] SEL;
output[3:0] INSTATUS;
/***********inout*****************/
inout[7:0] DATA;
// inout[15:0] DATA; //10/20
//wire sel;
reg wen;
//wire[7:0] dataout;
// reg[7:0] dataout;
// reg[7:0] din;
reg[7:0] din; //10/20 12/28 16
/*********************************/
wire LED_out ;
/*LCD display*/
//input[3:0] CUR;
output rw, rs ,SHIFT_CLK;
output en;
output [7:0] db;
//display2
output wire srw, srs ,sSHIFT_CLK;
output wire sen;
output wire[7:0] sdb;
/************/
output LOCKED_OUT;
//ram//
// output reg[7:0] SEVEN_SEG_DATA;
// output[4:1] SEL;
output SCK;
input load;
input store;
//input[DWIDTH-1:0] ewdata;
//output[DWIDTH-1:0] erdata;
reg[DWIDTH-1:0] ewdata;
reg[DWIDTH-1:0] erdata;
reg[DWIDTH-1:0] erdatanxt;
(* ramstyle="M9K" *) reg[DWIDTH-1:0] ram[WORDS-1:0];
reg[AWIDTH-1:0] addr;
reg[7:0] loadcnt;
reg[7:0] loadcntnxt;
reg[7:0] storecnt;
reg rsck;
reg [31:0] rsec_cnt ;//１秒作成用カウンタ
reg rsec1_flag ;//1秒のフラグ
reg rtoggle_flag ; //1秒ごとにトグルするフラグ
reg[3:0] enable_Seg;
reg[8:1] sel;
reg[7:0] seven_seg1_hold;
reg[7:0] seven_seg2_hold;
reg[7:0] seven_seg3_hold;
reg[7:0] seven_seg4_hold;
reg[7:0] seven_seg5_hold;
reg[7:0] seven_seg6_hold;
reg[7:0] seven_seg7_hold;
reg[7:0] seven_seg8_hold;
reg[7:0] seven_seg;
reg[3:0] enable_seg;
reg sck;
reg[3:0] seven_seg1_counter;
reg[3:0] seven_seg2_counter;
reg[3:0] seven_seg3_counter;
reg[3:0] seven_seg4_counter;
reg[3:0] seven_seg5_counter;
reg[3:0] seven_seg6_counter;
reg[3:0] seven_seg7_counter;
reg[3:0] seven_seg8_counter;
reg [31:0] sec_cnt ;//１秒作成用カウンタ
reg sec1_flag ;//1秒のフラグ
reg toggle_flag ; //1秒ごとにトグルするフラグ
reg [3:0] cur;//ステートレジスタ
reg [3:0] nxt;//ステート生成回路
reg [31:0] swchatcnt1;
reg swchatbuf1;
reg swchat1_flag;
reg swchat1_toggle;
reg sw1p;
reg [3:0] detcnt1;
reg sw1;
reg [31:0] swchatcnt2;
reg swchatbuf2;
reg sw2p;
reg [3:0] detcnt2;
reg sw2;
reg [31:0] swchatcnt3;
reg swchatbuf3;
reg [3:0] detcnt3;
reg sw3p;
reg sw3;
reg [31:0] swchatcnt4;
reg swchatbuf4;
reg [3:0] detcnt4;
reg sw4p;
reg sw4;
reg [31:0] swchatcnt5;
reg swchatbuf5;
reg [3:0] detcnt5;
reg sw5p;
reg sw5;
reg[31:0] chat_cnt;
reg chat_cnt_flag;
reg chat_cnt_toggle_flag;
reg normalout;
reg readidout;
reg readout;
reg writeout;
reg [31:0] rd_cnt1;
reg rd_cnt_flag1;
reg rd_clk1;
reg [15:0] rdid_cnt1;
reg rdid_cnt_flag1;
reg rdid_clk1;
reg rdidframe;
reg cle;
reg cen;
// reg wen;
reg ale;
reg ren;
reg wp ;
reg [23:0] cntw;
reg [7:0] next;
reg [7:0] tsw;
//reg [15:0] tsw;
reg wenspan;
//status register
reg[7:0] status_reg;
reg[15:0]r_cyc_count1;
reg[15:0]w_cyc_count1;
//reg[15:0]c_cyc_count1;
reg[9:0]e_cyc_count1;
reg[9:0]ecyc;
//addr //
reg[7:0] addrs1;
reg[7:0] addrs2;
//addr start//
reg[7:0] addrs3;
reg[7:0] addrs4;
//addr end
reg[7:0] addre3;
reg[7:0] addre4;
//use for Display addr//
reg[7:0] addrp1;
reg[7:0] addrp2;
reg[7:0] addrp3;
reg[7:0] addrp4;
reg[11:0] caddrs1;
reg[7:0] wdatain;
reg[16:0] adcyc;
reg[16:0] adcyccnt;
reg[15:0] counterseg1;
reg[15:0] counterseg2;
reg[15:0] counterseg3;
reg[15:0] counterseg4;
reg[3:0] instatus;
/**********************/
//PLL
wire RES_P;
wire hclk ;
wire hlocked;
/**********************/
//ram//
// parameter DWIDTH=36,AWIDTH=8,WORDS=256;
parameter DWIDTH=36,AWIDTH=8,WORDS=256;
parameter rF50M000_cnt=32'h000001f4 ;
// parameter rF50M000_cnt=32'h00060000 ;
parameter selinit_value =8'b10000000;
//
// parameter F50M000_cnt=32'h02FAF080 ;//1秒ごとの変化
parameter F50M000_cnt=32'h017D7840 ;//0.5秒ごとの変化
//parameter F50M000_rdcnt=32'h000009c4;//0.00001sec 10/1doukaku 10/18 write動作確認
parameter F50M000_rdcnt=32'h00000003; ///12/14/a 5Mhz動作/0.1usec 10Mhz 5 11/25動作せず//19 12/12動作//1a 動作12/12 //25/12/10動作//30 1.02MHz 動作//
// parameter F50M000_rdcnt=32'h0007a120; //10/3
// parameter F50M000_rdcnt=32'h000f4240;
// parameter F50M000_rdcnt=32'h017d7840;
parameter swchatcntof = 32'h00bebc20;//64
//parameter swchantcntofsw1 = 32'h005f5e10; //0.125secシミュレーター用 write動作確認1 ff-100
parameter swchantcntofsw1 = 32'h00bebc20; //0.125secシミュレーター用 write動作確認1 ff-100
// parameter swchantcntofsw1 = 32'h0000000ff; //シミュレーター用 write動作確認1 ff-100
//parameter swchantcntofsw1 = 32'h000000ff;
// parameter swchantcntofsw2 = 32'h004c4b40; //44aa20 0.09 4c4b40 0.1sec
parameter swchantcntofsw2 = 32'h00bebc20; //98960 0.09 4c4b40 0.2sec
// parameter swchantcntofsw2 = 32'h00000064; //シミュレーター用 write動作確認1 64
// parameter swchantcntofsw3 = 32'h000009c4; //ff
parameter swchantcntofsw3 = 32'h00016e360; //
// parameter swchantcntofsw3 = 32'h00000384;//44aa20/9c4 =708h 384h 1c2h
//parameter swchantcntofsw3 = 32'h00000064; //シミュレーター用 write動作確認1 64
/***********************/
parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
initial cur <=4'b0000;
initial toggle_flag <= 1'b1;
initial chat_cnt <=32'h00000000;
initial chat_cnt_flag <= 1'b1;
initial chat_cnt_toggle_flag <=1'b1;
initial sec_cnt <=32'h00000000;
initial sec1_flag <=1'b1;
initial rd_cnt1 <=32'h00000000;
initial rd_cnt_flag1 <= 1'b1;
initial rd_clk1 <= 1'b1;
//initial nxt <=2'b00;
//initial rdid_cnt1 <= 16'h0000;
// initial rdid_cnt_flag1 <=1'b1;
// initial rdid_clk1 <= 1'b1;
// initial rdidframe <=1'b1;
initial swchat1_flag<=1'b0;
initial swchat1_toggle<=1'b0;
initial swchatbuf1 <=1'b1;
initial swchatbuf2 <=1'b1;
initial swchatbuf3 <=1'b1;
initial swchatbuf4 <=1'b1;
initial detcnt1 <=4'b0000;
initial detcnt2 <=4'b0000;
initial detcnt3 <=4'b0000;
initial detcnt4 <=4'b0000;
initial detcnt5 <=4'b0000;
initial cle <= 1'b0;
initial cen <= 1'b1;
initial wen <= 1'b1;
initial ale <= 1'b0;
initial ren <= 1'b1;
initial wp <= 1'b1;
initial wenspan <= 1'b0;
initial cntw =24'h000000;
initial next = 8'b00000000;
initial tsw = 8'hZZ;
//initial tsw = 16'bZZZZZZZZZZZZZZZZ;
initial din = 8'b00000000;
initial r_cyc_count1=16'h0000;
initial w_cyc_count1 =16'h0000;
//initial c_cyc_count1 =16'h0000;
initial e_cyc_count1 =10'h0000;
initial adcyccnt =17'b00000000000000000;
initial addrs1 =8'b00000000;
initial addrs2 =8'b00000000;
//initial addrs3 =8'b00001000;//10/18動作確認済
initial addrs3 =8'b00000000;
initial addrs4 =8'b00000000;
initial addre3 =8'b00000000;
initial addre4 =8'b00000000;
// initial caddrs1=12'd0256; //256:100h(256まで) //83fh 12'b1000 0011 1111 d2111
initial caddrs1=12'h83f; //256:100h(256まで) //83fh 12'b1000 0011 1111 d2111
initial adcyc=17'h00000;
// initial ecyc=10'b0000000101; //max 3ff
initial ecyc=10'h3ff; //max 3ff
initial wdatain=8'b00000000;
initial storecnt=8'h00;
/********7seg **************/
//ram
initial loadcnt = 8'b00000000;//00000000
initial loadcntnxt = 8'b00000000;//00000000
initial instatus =4'b0000;
integer i;
initial begin
for(i=0;i<WORDS;i=i+1)
ram[i]=i;
end
initial rsck = 1'b0;
initial rsec1_flag =1'b0;
initial rtoggle_flag =1'b0;
initial rsec_cnt = 32'h00000000 ;
initial seven_seg1_counter = 4'h1;
initial seven_seg2_counter= 4'h2;
initial seven_seg3_counter= 4'h3;
initial seven_seg4_counter= 4'h4;
initial loadcnt = 8'b00000000;
//initial seven_seg1_hold =8'b1
assign RES_P = ~RST;
assign LOCKEDOUT = hlocked;
always@(posedge hclk)
begin
if(rsec_cnt == rF50M000_cnt) begin //もし3300万回数えたらカウンタをリセットする
rsec_cnt <= 32'h00000000 ;
rsec1_flag <= 1'b1; //SEC1_FLAGに1をセットする
end else begin
rsec_cnt <= rsec_cnt + 1 ;
rsec1_flag <= 1'b0 ;
end
end
/**********************/
/*1秒検出部 */
/**********************/
always@(posedge hclk)
begin
if(rsec1_flag == 1'b1 )begin
rtoggle_flag <= !rtoggle_flag ;
end
end
/**********************/
/*出力部 */
/**********************/
always@*
begin
rsck <= ~rtoggle_flag;
end
/**********************/
/*
always@(posedge hclk)
begin
addr<=ADDR;
end
*/
/*
always @(negedge RST or posedge rsck )
begin
if(RST ==1'b0)
begin
storecnt <= 8'b00000000;
end else begin
if(store==1'b0) begin
// ram[storecnt] <= ewdata;
// erdata <= ram[storecnt];
// storecnt <= storecnt + 1;
end else if(load==1'b0)begin
erdata <= ram[loadcnt];
loadcnt <= loadcnt +1;
end
end
end
*/
always@(posedge rsck or negedge RST)begin
if(RST == 1'b0 )begin
enable_seg <= 4'b0000;
end else if(enable_seg ==4'b0111)begin
enable_seg <= 4'b0000;
end else begin
enable_seg <= enable_seg +1'b1;
end
end
always@(posedge rsck or negedge RST)begin
if(RST == 1'b0 )begin
sel <= selinit_value;
end else begin
sel[2] <= sel[1] ; //シフト動作を開始する
sel[3] <= sel[2] ; //シフト動作を開始する
sel[4] <= sel[3] ; //シフト動作を開始する
sel[5] <= sel[4] ;
sel[6] <= sel[5] ; //シフト動作を開始する
sel[7] <= sel[6] ; //シフト動作を開始する
sel[8] <= sel[7] ; //シフト動作を開始する
sel[1] <= sel[8] ;
end
end
assign SEL[8:1] = sel[8:1];
always@(negedge RST or posedge hclk)
begin if(RST ==1'b0)begin
seven_seg1_hold <=8'b00000110;
seven_seg2_hold <=8'b01011011;
seven_seg3_hold <=8'b01001111;
seven_seg4_hold <=8'b01100110;
seven_seg5_hold <=8'b01101101;
seven_seg6_hold <=8'b01111101;
seven_seg7_hold <=8'b00100111;
seven_seg8_hold <=8'b00111111;
end else begin
// case(seven_seg1_counter)
// case(erdata[3:0])
// case(adcyccnt[3:0])
//case(w_cyc_count1[3:0])
case(addrp1[3:0])
4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg1_hold <= 8'b00000110;
endcase
//case(seven_seg2_counter)
// case(erdata[7:4])
//case(w_cyc_count1[7:4])
case(addrp1[7:4])
4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg2_hold <= 8'b01011011;
endcase
//case(seven_seg3_counter)
//case(loadcnt[3:0])
// case(adcyccnt[11:8])
//case(w_cyc_count1[11:8])
case(addrp2[3:0])
4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg3_hold <= 8'b01001111;
endcase
// case(seven_seg4_counter)
//case(loadcnt[7:4])
//case(adcyccnt[15:12])
//case(w_cyc_count1[15:12])
case(addrp3[3:0])
4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg4_hold <= 8'b01100110;
endcase
// case(adcyccnt[19:16])
//case(w_cyc_count1[3:0])
case(addrp3[7:4])
4'b0000 : seven_seg5_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg5_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : seven_seg5_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg5_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg5_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg5_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg5_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg5_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg5_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg5_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg5_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg5_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg5_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg5_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg5_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg5_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg5_hold <= 8'b01101101;
endcase
//case(seven_seg2_counter)
// case(erdata[7:4])
// case(adcyccnt[23:20])
//case(w_cyc_count1[7:4])
case(addrp4[3:0])
4'b0000 : seven_seg6_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg6_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg6_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg6_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg6_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg6_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg6_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg6_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg6_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg6_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg6_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg6_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg6_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg6_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg6_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg6_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg6_hold <= 8'b01111101 ;
endcase
//case(seven_seg3_counter)
//case(loadcnt[3:0])
// case(adcyccnt[27:24])
//case(w_cyc_count1[11:8])
case(addrp4[7:4])
4'b0000 : seven_seg7_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg7_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : seven_seg7_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg7_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg7_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg7_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg7_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg7_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg7_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg7_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg7_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg7_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg7_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg7_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg7_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg7_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg7_hold <= 8'b00100111;
endcase
// case(seven_seg4_counter)
//case(loadcnt[7:4])
//case(adcyccnt[31:28])
//case(w_cyc_count1[15:12])
case(addrp2[7:4])//固定low
4'b0000 : seven_seg8_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg8_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg8_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg8_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg8_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg8_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg8_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg8_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg8_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg8_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg8_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg8_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg8_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg8_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg8_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg8_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg8_hold <= 8'b01111111;
endcase
end
end
always@*
begin
case(enable_seg)
// 2'b00: seven_seg<=~seven_seg4_hold;
4'b0000: SEVEN_SEG_DATA <= ~seven_seg8_hold;
4'b0001: SEVEN_SEG_DATA<=~seven_seg1_hold;
4'b0010: SEVEN_SEG_DATA<=~seven_seg2_hold;
4'b0011: SEVEN_SEG_DATA<=~seven_seg3_hold;
4'b0100: SEVEN_SEG_DATA<=~seven_seg4_hold;
4'b0101: SEVEN_SEG_DATA<=~seven_seg5_hold;
4'b0110: SEVEN_SEG_DATA<=~seven_seg6_hold;
4'b0111: SEVEN_SEG_DATA<=~seven_seg7_hold;
// default: SEVEN_SEG_DATA <= 8'b00000000;
endcase
end
//
/*
seg7_01_01 U1(
.hclk(hclk), //.signal bottom(signal top),
.DATA(DATA),
.RST(RST),
.SEVEN_SEG_DATA(SEVEN_SEG_DATA),
.SEL(SEL),
.EN(EN)
);
*/
/*************************/
/*************LCD display**************************/
lcd_sc1602_06_4b_01 U2( //.signal bottom(signal top),
//.hclk(hclk),
.CLK(hclk),
.DATA(DATA),
.RST(RST),
.CUR(cur),
.rw(rw),
.rs(rs),
.en(en),
.db(db),
.addrs1(addrp1),
.addrs2(addrp2),
.addrs3(addrp3),
.addrs4(addrp4),
.wdatain(wdatain),
.EN(EN),
.INSTATUS(instatus)
);
lcd_sc1602_06_4b_01ch01 U3( /////////////////////compare check display
//.hclk(hclk),
.CLK(hclk),
.DATA(DATA),
.RST(RST),
.CUR(cur),
.rw(srw),
.rs(srs),
.en(sen),
.db(sdb),
.addrs1(addrp1),
.addrs2(addrp2),
.addrs3(addrp3),
.addrs4(addrp4),
.wdatain(wdatain),
.EN(sEN),
.erdata(erdata),
.erdatanxt(erdatanxt),
.loadcnt(loadcnt),
.loadcntnxt(loadcntnxt)
);
//parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
//parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
always@(posedge hclk)
begin
if(sw1 || sw2 || sw3 || sw4)begin
adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}; //12/28
end else
if(cur==4'b0011)begin // READPAGE c change a change
if(adcyccnt[15:0]==16'h00)begin
addrp1<= r_cyc_count1[7:0];
addrp2<= r_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= r_cyc_count1[7:0];
addrp2<= r_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end else if(cur==4'b0100)begin //ERACE BLOCK achange
if(e_cyc_count1[9:0]==10'b0000000000)begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
{addrp4,addrp3}<={addrs4,addrs3}+{e_cyc_count1[9:0],6'b000000};
end
end else if(cur==4'b0101)begin //program page c change a change
if(adcyccnt[15:0]==16'h00)begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end else if(cur==4'b1000)begin //compare CHECK c cahge a chagen
if(adcyccnt[15:0]==16'h00)begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end else if(cur==4'b1001)begin //AdSel start old status was Addselect 1001
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3; //input start addr
addrp4<=addrs4; //input start addr
end else if(cur==4'b1010)begin //AdSel end
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addre3; //input end addr
addrp4<=addre4; //input end addr
end else if(cur==4'b1011)begin //Adcycl 1100
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
{addrp4,addrp3} <= adcyc[15:0];
end else if(cur==4'b1100)begin //Datainput 1010
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3; //input addr
addrp4<=addrs4; //input addr
end else if(cur==4'b1110)begin //ErsPrgCom 1110
if(instatus == 4'b0001 )begin //instatus /4'b0001 Erase /4'b0010 Program /4'b0100 CompareCheck
if(e_cyc_count1[9:0]==10'b0000000000)begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
{addrp4,addrp3}<={addrs4,addrs3}+{e_cyc_count1[9:0],6'b000000};
end
end else if(instatus == 4'b0010 || instatus == 4'b0100)begin
if(adcyccnt[15:0]==16'h00)begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
addrp3<=addrs3;
addrp4<=addrs4;
end else begin
addrp1<= w_cyc_count1[7:0];
addrp2<= w_cyc_count1[15:8];
{addrp4,addrp3}<={addrs4,addrs3}+adcyccnt[15:0];
end
end
end else begin
addrp1<=caddrs1[7:0];
addrp2<=caddrs1[11:8];
addrp3<=addrs3;
addrp4<=addrs4;
end
end
assign LED_out = toggle_flag ;
/******************************************************************************/
/*****************readcycle counter*******************************/
always@(posedge hclk)
begin
if(rd_cnt1 == F50M000_rdcnt) begin //もし3300万回数えたらカウンタをリセットする
rd_cnt1 <= 32'h00000000 ;
rd_cnt_flag1 <= 1'b1; //SEC1_FLAGに1をセットする
end else begin
rd_cnt1 <= rd_cnt1 + 1 ;
rd_cnt_flag1 <= 1'b0 ;
end
end
/**********************/
/*1秒検出部 */
/**********************/
always@(posedge hclk)
begin
if(rd_cnt_flag1 == 1'b1 )begin
rd_clk1 <= !rd_clk1 ;
end
end
/*****************^end readcycle counter*******************************/
/**********************/
/*LED出力部 */
/**********************/
// assign LED_rdout = rd_clk1 && rdidframe; //9/30
assign LED_rdout = rd_clk1 ;
/*************************************************/
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0)
cur <= NORMAL;
else
cur <= nxt;
end
always@(posedge hclk)
begin
if(chat_cnt == swchatcntof) begin //
chat_cnt <= 32'h00000000 ;
chat_cnt_flag <= 1'b1; //SEC1_FLAGに1をセットする
end else begin
chat_cnt <= chat_cnt + 1 ;
chat_cnt_flag <= 1'b0 ;
end
end
always@(posedge hclk)
begin
if(chat_cnt_flag == 1'b1 )begin
chat_cnt_toggle_flag <= !chat_cnt_toggle_flag ;
end
end
assign CLED_out = chat_cnt_toggle_flag ;
/************************************************************************/
// always@(negedge rd_clk1 or negedge RST)begin
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt1 <= 32'h00000000 ;
// end else if(swchatcnt1 == swchatcntof)begin
end else if(swchatcnt1 == swchantcntofsw1)begin
swchatcnt1 <= 32'h00000000 ;
swchat1_flag<= 1'b1;
end else begin
swchatcnt1 <= swchatcnt1 + 1 ;
swchat1_flag<=1'b0;
end
end
always@(posedge hclk)
begin
if(swchatcnt1 == 1'b1 )begin
swchat1_toggle<= !swchat1_toggle;
end
end
always@(posedge hclk)begin
//always@(posedge hclk )begin
// always@(negedge chat_cnt_toggle_flag)begin
if(swchatcnt1 == 32'h00000000 ) begin
// swchatbuf1 <= SW1;
// sw1 <= ~swchatbuf1 && ~SW1;
sw1 <= ~SW1; //20/01/27
end else
sw1 <= 1'b0;
end
assign SW1OUT = sw1;
/************************************************************************/
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt2 <= 32'h00000000 ;
// end else if(swchatcnt1 == swchatcntof)begin
end else if(swchatcnt2 == swchantcntofsw2)begin
// end else if(swchatcnt2 == swchatcntof)begin // 10/15
swchatcnt2 <= 32'h00000000 ;
end else begin
swchatcnt2 <= swchatcnt2 + 1 ;
end
end
always@(posedge hclk )begin
// always@(negedge chat_cnt_toggle_flag)begin
if(swchatcnt2 == 32'h00000000 ) begin
// swchatbuf2 <= SW2;
// sw2 <= ~swchatbuf2 && ~SW2;
sw2 <= ~SW2; //2001/27
end else
sw2 <= 1'b0;
end
/************************************************************************/
//always@(posedge hclk or negedge RST)begin //12/28
always@(posedge rd_clk1 or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt3 <= 32'h00000000 ;
// end else if(swchatcnt3 == swchantcntofsw1)begin
//9/30
end else if(swchatcnt3 == swchantcntofsw3)begin
swchatcnt3 <= 32'h00000000 ;
end else begin
swchatcnt3 <= swchatcnt3 + 1 ;
end
end
/*
//always@(posedge SW3 or posedge rd_clk1)begin//12/28
always@(posedge rd_clk1)begin//12/28
// always@(posedge rd_clk1)begin
// always@(negedge chat_cnt_toggle_flag)begin
if(rd_clk1 ) begin
swchatbuf3 <= SW3;
sw3 <= ~swchatbuf3;
// sw3 <= ~SW3;
end else
swchatbuf3<=1'b1;
sw3 <= 1'b0;
end
*/
//always@(posedge SW3 or posedge rd_clk1)begin//12/28
always@(posedge rd_clk1)begin//12/28
// always@(posedge rd_clk1)begin
// always@(negedge chat_cnt_toggle_flag)begin
if(swchatcnt3==32'h00000000 ) begin
// swchatbuf3 <= SW3;
// sw3 <= ~swchatbuf3 && ~SW3; //20/1/27
sw3 <= ~SW3;
end else
//swchatbuf3<=1'b1;
sw3 <= 1'b0;
end
assign SW3OUT =sw3;
/************************************************************************/
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt4 <= 32'h00000000 ;
end else if(swchatcnt4 == swchatcntof)begin
swchatcnt4 <= 32'h00000000 ;
end else begin
swchatcnt4 <= swchatcnt4 + 1 ;
end
end
always@(posedge hclk )begin
//always@(posedge rd_clk1 )begin
if(swchatcnt4 == 32'h00000000 ) begin
// swchatbuf4 <= SW4;
// sw4 <= ~swchatbuf4 && ~SW4;
sw4<= ~SW4 ;
end else
sw4 <= 1'b0;
end
/************************************************************************/
always@(posedge hclk or negedge RST)begin
if(RST == 1'b0 ) begin
swchatcnt5 <= 32'h00000000 ;
end else if(swchatcnt5 == swchatcntof)begin
swchatcnt5 <= 32'h00000000 ;
end else begin
swchatcnt5 <= swchatcnt5 + 1 ;
end
end
always@(posedge hclk )begin
if(swchatcnt5 == 32'h00000000 ) begin
// swchatbuf5 <= SW5;
// sw5 <= ~swchatbuf5 && ~SW5;
sw5<=~SW5;
end else
sw5 <= 1'b0;
end
/************************************************************************/
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
//always@(cur or sw1 or sw2 or sw3)begin
always@( posedge cur[0] or posedge cur[1] or posedge cur[2] or posedge cur[3] or posedge sw1 or posedge sw2 )begin
case(cur)
NORMAL:if(sw1) //3'b000
nxt <= READID ;
else
nxt <= NORMAL;
READID:if(sw1) //3'b001
nxt <= NORMAL ;
else if(sw2)
nxt <= READSTATUS;
else
nxt <= READID;
READSTATUS:if(sw1) //3'b010
nxt <= NORMAL ;
else if(sw2)
nxt <= READPAGE;
else
nxt <= READSTATUS;
READPAGE:if(sw1) //3'b011
nxt <= NORMAL ;
else if(sw2)
nxt <= ERASEBLOCK;
else
nxt <= READPAGE ;
ERASEBLOCK:if(sw1) //
nxt <= NORMAL ;
else if(sw2)
nxt <= PROGRAMPAGE;
else
nxt <= ERASEBLOCK ;
PROGRAMPAGE:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= READPARAMPAGE;
else
nxt <= PROGRAMPAGE ;
READPARAMPAGE:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= READUNIID;
else
nxt <= READPARAMPAGE ;
READUNIID:if(sw1)
nxt <= NORMAL ;
else if(sw2)
// nxt <= READID;
nxt <=COMPARECHECK;
else
//parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,
//READUNIID=4'b0111,COMPARECHECK=4'b1000,AdSel Start=4'b1001,AdSel End 4'b1010 ,Adcycl =4'b1011,Data Input=4'b1100,Load=4'b1101,;
nxt <= READUNIID ;
COMPARECHECK:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= AdSelStart;
else
nxt <= COMPARECHECK ;
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
AdSelStart:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= AdSelEnd;
else
nxt <= AdSelStart ;
AdSelEnd:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= Adcycl;
else
nxt <= AdSelEnd ;
Adcycl:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= DataInput;
else
nxt <= Adcycl ;
DataInput:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= Load;
else
nxt <= DataInput ;
Load:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= ErsPrgCom;
else
nxt <= Load ;
ErsPrgCom:if(sw1)
nxt <= NORMAL ;
else if(sw2)
nxt <= READID;
else
nxt <= ErsPrgCom ;
default:nxt <=4'b0000;
endcase
end
assign STATUSLEDOUT[3:0] = ~cur[3:0] ;
//assign DATA = (cle ||ale||~wen)?tsw:8'hzz; //10/10動作している11/30
assign DATA = (cle ||ale||wenspan)?tsw:8'hzz; //10/10動作している
//assign DATA = (cle ||ale||wenspan)?dataout:8'hzz; //12/28実験
//assign DATA = (cle ||ale)?tsw:8'hzz;// 10/22~11/22まではこれで動作している
always@(posedge ren)
begin
//if(rd_clk1)
din <= DATA ;
end
//always@(posedge wenspan or posedge cle posedge ale)
/*always@(wen)
if(cle ==1'b1||ale ==1'b1||wenspan==1'b1)begin
//if(rd_clk1)
dataout <= tsw ;
end else begin
dataout <=8'hzz;
end
*/
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
//always@(posedge SW3 or negedge RST)
always@(posedge sw3 or negedge RST)
begin
if(RST == 1'b0 ) begin
addrs4 <= 8'h00 ;
addre4<=8'h00;
end else if(cur[3:0] ==4'b1001 )begin
if(SW5==1'b0)begin
addrs4 <= addrs4 - 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end else begin
addrs4 <= addrs4 + 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end
end else if(cur[3:0] ==4'b1010 )begin
if(SW5==1'b0)begin
addre4 <= addre4 - 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end else begin
addre4 <= addre4 + 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end
end else if(cur[3:0] ==4'b1100)begin
if(SW5==1'b0)begin
wdatain[7:4]<= wdatain[7:4] -1;
end else begin
wdatain[7:4]<= wdatain[7:4] +1;
end
end
end
//always@(posedge SW4 or negedge RST)
always@(posedge sw4 or negedge RST)
begin
if(RST == 1'b0 ) begin
addrs3 <= 8'h00 ;
addre3<= 8'h00;
// erdata <= ram[0];
loadcnt <= 8'b00000000;
end else if(cur[3:0] ==4'b1001 )begin //AdSelStart
if(SW5==1'b0)begin
addrs3 <= addrs3 - 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end else begin
addrs3 <= addrs3 + 1;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end
end else if(cur[3:0] ==4'b1010 )begin //AdSelEnd
if(SW5==1'b0)begin
addre3 <= addre3 - 1 ;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end else begin
addre3 <= addre3 + 1;
// adcyc[15:0]<={addre4[7:0],addre3[7:0]}-{addrs4[7:0],addrs3[7:0]}+1;
end
end else if(cur==4'b1100)begin
if(SW5==1'b0)begin
wdatain[3:0]<= wdatain[3:0] -1;
end else begin
wdatain[3:0]<= wdatain[3:0] +1;
end
end else if(cur==4'b1101)begin
if(SW5==1'b0)begin
// erdata <= ram[loadcnt];
loadcnt[7:0] <= loadcnt[7:0] -1;
end else begin
// erdata <= ram[loadcnt];
loadcnt[7:0] <= loadcnt[7:0] +1;
end
end
end
always@(posedge hclk)
begin
erdata <= ram[loadcnt];
erdatanxt <= ram[loadcnt+1];
loadcntnxt <= loadcnt+1;
end
always @( posedge rd_clk1) begin
if ( RST==1 'b0 ) begin
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan<= 1'b0;
tsw <= 8 'h00;
adcyccnt <= 17'h000;
// tsw <= 16 'h0000;
cntw <= 24 'h0000000;
next <= 8'd0;
r_cyc_count1<=16'h0000;
w_cyc_count1<=16'h0000;
instatus<=4'b0000;
// c_cyc_count1<=16'h0000;
for(i=0;i<WORDS;i=i+1) ram[i]=0; // 11/20
end else if (cntw == 24 'h000064 )begin
cntw <= 24 'h0000;
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
end else if(sw3 ==1'b1 && cur[3:0] ==4'b0001 )begin //ReadID
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
next <=8'd1;
cntw <= 24 'h0000;
end else if(sw3 ==1'b1 && cur[3:0] == 4'b0010)begin //Read Status
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
next <=8'd30;
cntw <= 24'h0000;
end else if(sw3 ==1'b1 && cur[3:0] == 4'b0011)begin //read page
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
next <=8'd40;
cntw <= 24'h0000;
//11/20
end else if(sw3 ==1'b1 && cur[3:0]== 4'b0100)begin //ERASE BLOCK
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
cntw <= 24'h0000;
next <=8'd70;
end else if(sw3 ==1'b1 && cur[3:0]== 4'b0101)begin //PROGRAM PAGE
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
// adcyccnt <= 16'h00;
cntw <= 24'h0000;
next <=8'd100;
end else if(sw3 ==1'b1 && cur[3:0]== 4'b1000)begin //COMPARECHECK
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
next <=8'd140;
end else if(sw3 ==1'b1 && cur[3:0]== 4'b1110)begin //ErsPrgCom
for(i=0;i<WORDS;i=i+1) ram[i]=0;
storecnt =8'h00;
cntw <= 24'h0000;
next <=8'd70;
end else begin
cntw <= cntw + 1'b1;
case (next)
8'd254 :if ( cntw == 24 'd2) begin //1/5/ d2
if(RB == 1'b0)begin
next <=8'd254;
end else begin
if(cur[3:0]==4'b0011)begin //read page
// if(adcyccnt == adcyc )begin
if(adcyccnt > adcyc )begin // 12/15
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
adcyccnt <= 17'h000;
// r_cyc_count1 <= 16'h00;
next <=8'd00;
// end else if(adcyccnt < adcyc)begin
end else if(adcyccnt < adcyc||adcyccnt == adcyc)begin
//read page
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
//tsw <= 8 'h0000;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt +1;
next <=8'd40;
end
end else if(cur[3:0]==4'b0100)begin //eraseblock
if(e_cyc_count1 == ecyc )begin
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
adcyccnt <= 16'h00;
e_cyc_count1 <= 10'b0000000000;
next <=8'd00;
end else if( e_cyc_count1<ecyc)begin //ffbf dec 65471 65535-64
//read page
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
//tsw <= 8 'h0000;
cntw <= 24 'h000000;
e_cyc_count1 <= e_cyc_count1 + 1 ;
next <=8'd70;
end
end else if(cur[3:0]==4'b0101)begin //program PAGE
// if(DATA == 8'he0 ||DATA == 8'hc0)begin
// if(adcyccnt == adcyc )begin
if(adcyccnt > adcyc )begin // 12/15
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
adcyccnt <= 16'h00;
// w_cyc_count1 <=16'h00;
next <=8'd00;
// end else if(adcyccnt < adcyc)begin
end else if(adcyccnt < adcyc||adcyccnt == adcyc)begin
//read page
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
//tsw <= 8 'h0000;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt+1 ;
next <=8'd100;
end
//end else begin
// next<=8'd254;
// end
end
if(cur[3:0]==4'b1000)begin //COMPARECHECK=4'b1000
// if(adcyccnt == adcyc )begin
if(adcyccnt > adcyc )begin // 12/15
/* if(din != wdatain)begin
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din[7:0]};
// storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
adcyccnt <= 16'h00;
// c_cyc_count1<=16'h00;
next <=8'd00;
end else begin*/
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
adcyccnt <= 16'h00;
// c_cyc_count1<=16'h00;
next <=8'd00;
// end
// end else if(adcyccnt < adcyc)begin
end else if(adcyccnt < adcyc||adcyccnt == adcyc)begin
/* if(din != wdatain)begin
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din[7:0]};
// storecnt <= storecnt + 1;
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'h0000;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt +1;
// c_cyc_count1<=16'h00;
next <=8'd140;
end else begin*/
//read page
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
//tsw <= 8 'h0000;
cntw <= 24 'h000000;
// adcyccnt <= adcyccnt +1;
next <=8'd140;
// end
end
end
if(cur[3:0]==4'b1110)begin
if(instatus == 4'b0001)begin
if(e_cyc_count1 == ecyc )begin
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24'h000000;
adcyccnt <= 16'h00;
e_cyc_count1 <= 10'b0000000000;
next <=8'd100;
end else if( e_cyc_count1 < ecyc )begin //ffbf dec 65471 65535-64
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24'h000000;
e_cyc_count1 <= e_cyc_count1 + 1 ;
next <=8'd70;
end
end else if(instatus == 4'b0010)begin
if(adcyccnt > adcyc )begin // 12/15
cntw <= 24 'h000000;
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24'h000000;
adcyccnt <= 16'h0000;
w_cyc_count1<=16'h0000;
next <=8'd140;
end else if(adcyccnt < adcyc||adcyccnt == adcyc)begin
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
cntw <= 24'h000000;
next <=8'd100;
end
end else if(instatus == 4'b0100)begin
if(adcyccnt > adcyc )begin // 12/15
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
w_cyc_count1<=16'h0000;
adcyccnt <= 16'h0000;
instatus <=4'b0000;
next <=8'd00;
end else if(adcyccnt < adcyc||adcyccnt == adcyc)begin
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
cntw <= 24 'h000000;
next <=8'd140;
end
end
end
end
end
// 8'd0:if(cntw ==24'd2)begin
// instatus <=4'b0000;
// end
8'd1 : if ( cntw == 24 'd3) begin // cntw==247d0だと動作しない。
// 8'd1 : if ( cntw == 24 'd0) begin //
// 8'd1 : if ( rdid_clk1 ==1'b1) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b0;
tsw <= 8 'hzz;
//tsw <= 16 'hzzzz;
cntw <= 24 'h000000;
next <= 8'd2;
end
8'd2 : if ( cntw == 24 'd1 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hff;
// tsw <= 16 'h00ff;
cntw <= 24 'h000000;
next <= 8'd3;
end
8'd3 : if ( cntw == 24 'd1 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hff; //dataout ffh
// tsw <= 16 'h00ff;
cntw <= 24 'h000000;
next <= 8'd4;
end
8'd4 : if ( cntw == 24 'd4 ) begin //8
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hff;
// tsw <= 16 'h00ff;
cntw <= 24 'h000000;
next <= 8'd5;
end
8'd5 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
// tsw <= 16 'hzzzz;
cntw <= 24 'h000000;
next <= 8'd6;
end
/////////////////////////command end///////////////////////////
8'd6 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h90;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd7;
end
8'd7 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h90;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd8;
end
8'd8 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h90;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd9;
end
8'd9 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd10;
end
8'd10 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd11;
end
8'd11 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd12;
end
8'd12 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd13;
end
8'd13 : if ( cntw == 24 'd21 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd14;
end
8'd14 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd15;
end
8'd15 : if ( cntw == 24 'd4 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;// read trigger initiarize
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd16;
end
8'd16 : if ( cntw == 24 'd4 ) begin //rs_enb
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 1Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd17;
end
8'd17 : if ( cntw == 24 'd4 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;// read trigger initiarize
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd18;
end
8'd18 : if ( cntw == 24 'd4 ) begin //rs_enb
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 1Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd19;
end
8'd19 : if ( cntw == 24 'd4 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;// read trigger initiarize
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd20;
end
8'd20 : if ( cntw == 24 'd4 ) begin //rs_enb
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 1Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd21;
end
8'd21 : if ( cntw == 24 'd4 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;// read trigger initiarize
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd22;
end
8'd22 : if ( cntw == 24 'd4 ) begin //rs_enb
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 1Byte
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd23;
end
8'd23 : if ( cntw == 24 'd12 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b1;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
next <= 8'd255;
end
8'd255 : if ( cntw == 24 'd1 ) begin/////////////////////////////////////////////////////////////////////////////////////////////////////8'd255
cle <= 1'b0;
cen <= 1'b1;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
tsw <= 8 'h00;
cntw <= 24 'h000000;
// w_cyc_count1 <= 16'h0000; //11/3
// r_cyc_count1 <= 16'h0000; //11/3
// rdidframe<=1'b0;
next <= 8'd00;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
8'd30 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd31;
end
8'd31 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd32;
end
8'd32 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd33;
end
8'd33 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd34;
end
8'd34 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd35;
end
8'd35 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd36;
end
8'd36 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd37;
end
8'd37 : if ( cntw == 24 'd21 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd38;
end
8'd38 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd39;
end
8'd39 : if ( cntw == 24 'd2 ) begin
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd255;
end
8'd40 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
r_cyc_count1<=16'h0000;
next <= 8'd41;
end
8'd41 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd42;
end
8'd42 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd43;
end
8'd43 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd44;
end
8'd44 : if ( cntw == 24 'd6 ) begin //LSB
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw<=r_cyc_count1[7:0];
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 8'd45;
end
8'd45 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw<= r_cyc_count1[7:0];
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 8'd46;
end
8'd46 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd47;
end
8'd47 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= r_cyc_count1[15:8];
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 8'd48;
end
8'd48 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= r_cyc_count1[15:8];
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 8'd49;
end
8'd49 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd50;
end
8'd50 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs3+adcyccnt[7:0];
// tsw <= addrs3;
cntw <= 24 'h000000;
next <= 8'd51;
end
8'd51 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs3+adcyccnt[7:0];
// tsw <= addrs3;
cntw <= 24 'h000000;
next <= 8'd52;
end
8'd52 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd53;
end
8'd53 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
// tsw <= addrs4;
cntw <= 24 'h000000;
next <= 8'd54;
end
8'd54 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
// tsw <= addrs4;
cntw <= 24 'h000000;
next <= 8'd55;
end
8'd55 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd56;
end
8'd56 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd57;
end
8'd57 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd58;
end
8'd58 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd59;//11/23 12/28 d62
end
8'd59 : if ( cntw == 24 'd21 ) begin
if(RB == 1'b0)begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
cntw <= 24 'h000000;
next<=8'd58; //
end else begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
// r_cyc_count1<=16'h0000;
// adcyccnt<=16'h0000;
next <= 8'd62;
end
end
8'd60 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd61;
end
8'd61:if(cntw==24'd1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b0;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd61;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd62;
end
end
8'd62:if(cntw==24'd5)begin
// if(r_cyc_count1 < 16'h0003)begin
// if(r_cyc_count1 < caddrs1 )begin ///<=
// if(adcyccnt < adcyc +1)begin
if(r_cyc_count1 < caddrs1 || r_cyc_count1 == caddrs1)begin ///<=
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd63;
// end else if (r_cyc_count1 ==16'h0003)begin
// end else if (r_cyc_count1 == caddrs1)begin //+1
end else if (r_cyc_count1 > caddrs1 )begin //+1 //11/30==
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
adcyccnt <= adcyccnt +1;//11/24
// r_cyc_count1 <= 16'h0000;
next <=8'd254;//62
// end else if (r_cyc_count1 == caddrs1+1 && adcyc ==adcyccnt)begin //+1
/* end else if (r_cyc_count1 == caddrs1+1 )begin //+1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
// adcyccnt<=16'h0000;
adcyccnt <= adcyccnt +1;//11/24
r_cyc_count1 <= 16'h0000;
next <=8'd255;
*/
end
end
8'd63:if(cntw==24'd4)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd64;
end
8'd64:if(cntw==24'd1) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
r_cyc_count1 <=r_cyc_count1 +1;
next <= 8'd61; //62 11/19
end
8'd70 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h60;
instatus<= 4'b0001;
//adcyccnt<=16'h0000;
//e_cyc_count1<=10'b0000000000;
cntw <= 24 'h000000;
next <= 8'd71;
end
8'd71 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h60;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd73;
end
8'd73 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h60;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd74;
end
8'd73 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd74;
end
8'd74 : if ( cntw == 24 'd6 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000 + e_cyc_count1[1:0];
tsw<= {addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0]};
// tsw <= addrs3;
cntw <= 24 'h000000;
next <= 8'd75;
end
8'd75 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000 + e_cyc_count1[1:0];
tsw<= {addrs3[7:6]+e_cyc_count1[1:0],addrs3[5:0]};
// tsw <= addrs3;
cntw <= 24 'h000000;
next <= 8'd76;
end
8'd76 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd77;
end
8'd77 : if ( cntw == 24 'd6 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000 + e_cyc_count1[9:2];
tsw<=addrs4+e_cyc_count1[9:2];
// tsw <= addrs4;
cntw <= 24 'h000000;
next <= 8'd78;
end
8'd78 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000 + e_cyc_count1[9:2];
tsw<=addrs4+e_cyc_count1[9:2];
// tsw <= addrs4;
cntw <= 24 'h000000;
next <= 8'd79;
end
8'd79 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd86;
end
8'd86 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hd0;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd87;
end
8'd87 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hd0;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd88;
end
8'd88 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hd0;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd89;
end
8'd89 : if ( cntw == 24 'd21 ) begin //d2 12/15
if(RB == 1'b0)begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
next<= 8'd88;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
next<= 8'd89;
next <= 8'd90;
end
end
8'd90 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd91;
end
8'd91 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd92;
end
8'd92 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd93;
end
8'd93 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'hzz;//1210
tsw <= 8'h0000;
cntw <= 24 'h000000;
next <= 8'd94;
end
8'd94 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd95;
end
8'd95 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd96;
end
8'd96 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd97;
end
8'd97 : if ( cntw == 24 'd21 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd98;
end
8'd98 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd99;//254 12/10
end
8'd99:if(cntw ==24'd2)begin //12/10
if(din ==8'h80||din==8'hc0)begin
next <= 8'd97;
end else if(din ==8'he0)begin
next <=8'd254;
end
end
//////////////////////////////////ERASE BLOCK end///////////////////////////////////
////////////////////////////////////////////////////
//////////////////////////////PROGRAM PAGE START ////////////////0x05//////////////////////////////////////////////////////////////////////////////////////////program
8'd100 : if ( cntw == 24 'd3 ) begin ////d30 b12/10
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h80;
instatus<=4'b0010;
w_cyc_count1<=16'h0000;
// c_cyc_count1<=16'h0000;
cntw <= 24 'h000000;
next <= 8'd101;
end
8'd101 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h80;
cntw <= 24 'h000000;
next <= 8'd102;
end
8'd102 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h80;
cntw <= 24 'h000000;
next <= 8'd103;
end
8'd103 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd104;
end
8'd104 : if ( cntw == 24 'd6 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs1;//+w_cyc_count1[7:0];
cntw <= 24 'h000000;
next <= 8'd105;
end
8'd105 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs1;//+w_cyc_count1[7:0];
cntw <= 24 'h000000;
next <= 8'd106;
end
8'd106 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd107;
end
8'd107 : if ( cntw == 24 'd4 ) begin //6//12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs2;//+w_cyc_count1[15:8];
cntw <= 24 'h000000;
next <= 8'd108;
end
8'd108 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs2;//+w_cyc_count1[15:8];
cntw <= 24 'h000000;
next <= 8'd109;
end
8'd109 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd110;
end
8'd110 : if ( cntw == 24 'd4 ) begin //6//12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 8'd111;
end
8'd111 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 8'd112;
end
8'd112 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd113;
end
8'd113 : if ( cntw == 24 'd4 ) begin //6//12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 8'd114;
end
8'd114 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 8'd115;
end
8'd115 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
// tsw <= wdatain; //12/28
cntw <= 24 'h000000;
next <= 8'd116; //116//119 //12/9変更
end
//////////////////////////////////////////
8'd116 : if ( cntw == 24 'd4 ) begin //d26 12/15 //12/9 d35で動作 計算上の限界はale lowからd28 ここはd26 d35 12/28 03ならd26でもOK 12/30 02 d4でNG
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
cntw <= 24 'h000000;
next<=8'd115;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;// 12/9 1'b0//12/28
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw<=8 'hzz; //wdatain から変更/12/28hzz->wdatain
// tsw<=wdatain;
cntw <= 24 'h000000;
next <= 8'd119; //12/9 d117から変更
end
end
8'd117 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
// tsw <= 8 'haa;
// tsw<= w_cyc_count1[7:0];
// tsw<= w_cyc_count1[15:0];
tsw<=wdatain;
cntw <= 24 'h000000;
next <= 8'd118;
end
8'd118:if(cntw==24'd2)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//
wp <= 1'b1;
wenspan <= 1'b0;
//tsw <= 8 'haa;
//tsw<= w_cyc_count1[7:0];
//tsw<= w_cyc_count1[15:0];
tsw<=wdatain;
cntw <= 24 'h000000;
next <= 8'd119;
end
// 8'd119 : if ( cntw == 24 'd2 ) begin
// 8'd119 : if ( cntw == 24 'd35 ) begin//25 計算上の限界はale lowからd28 ここはd26 ｄ１１６で待たせるようにしたからd4で良い
8'd119 : if ( cntw == 24 'd16 )begin //d4 //12/11 1/2 01 ならd40でOK
// if(w_cyc_count1 < 16'h0003)begin
// if(adcyccnt < adcyc +1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b0;
tsw<=8'hzz;
cntw <= 24 'h000000;
next <= 8'd116;
end else
if(w_cyc_count1 < caddrs1 || w_cyc_count1 == caddrs1 )begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;//122/8 1
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b1;
tsw<=wdatain;
// tsw<= w_cyc_count1[7:0];
cntw <= 24 'h000000;
next<=8'd122;
end else if (w_cyc_count1 > caddrs1)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b1;
tsw <= wdatain;
cntw <= 24 'h000000;
adcyccnt <= adcyccnt +1;//11/24
next <= 8'd124;
end
end
8'd122 : if ( cntw == 24 'd4 ) begin //d4 12/11 12/12 d4 12/28
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
wenspan <= 1'b1;
tsw <= wdatain; //12/12
// tsw<= w_cyc_count1[7:0];
// tsw <= 16 'hzzzz; //12/01
cntw <= 24 'h000000;
next <= 8'd123;
end
8'd123:if(cntw==24'd2)begin //d2 12/11
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
wenspan <= 1'b0;
tsw<=8'hzz;
cntw <= 24 'h000000;
next <= 8'd122;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
wenspan <= 1'b0;
tsw <= 8 'hzz;
// tsw <= 16 'hzzzz;
cntw <= 24 'h000000;
w_cyc_count1 <= w_cyc_count1 +1;
next <= 8'd119;
end
end
8'd124 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h15;//12/28 10h
wenspan <= 1'b0;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd125;
end
8'd125 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h15;//12/28 10h
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd126;
end
8'd126 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h15;//12/28 10h
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd127;
end
8'd127 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd128;
end
8'd128 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;//12/28
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd129;
end
8'd129 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd130;
end
8'd130 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd131;
end
8'd131 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'hzz;//1210
tsw <= 8'h0000;
cntw <= 24 'h000000;
next <= 8'd132;
end
8'd132 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd133;
end
8'd133 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd134;
end
8'd134 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd135;
end
8'd135 : if ( cntw == 24 'd4 ) begin //1/3 d21
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd136;
end
8'd136 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd137;//254 12/10
end
8'd137:if(cntw ==24'd2)begin //12/10 d2/12/15 d21 12/24
if(din ==8'h80||din==8'hc0)begin
next <= 8'd135;
end else if(din ==8'he0)begin
next <=8'd254;
// end else begin //12/17
// next <=8'd254; //12/17
end
end
8'd140 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
instatus<=4'b0100;
w_cyc_count1<=16'h0000;
// c_cyc_count1<=16'h0000;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd141;
end
8'd141 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd142;
end
8'd142 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h00;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd143;
end
8'd143 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd144;
end
8'd144 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 8'd145;
end
8'd145 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw<= addrs1;
cntw <= 24 'h000000;
next <= 8'd146;
end
8'd146 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd147;
end
8'd147 : if ( cntw == 24 'd6 ) begin //disp_clear //6/12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 8'd148;
end
8'd148 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs2;
cntw <= 24 'h000000;
next <= 8'd149;
end
8'd149 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd150;
end
8'd150 : if ( cntw == 24 'd6 ) begin //disp_clear //6/12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
// tsw <= 8 'h0001;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 8'd151;
end
8'd151 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
// tsw <= 8 'h0001;
tsw <= addrs3+adcyccnt[7:0];
cntw <= 24 'h000000;
next <= 8'd152;
end
8'd152 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd153;
end
8'd153 : if ( cntw == 24 'd6 ) begin //disp_clear //6/12/12
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 8'd154;
end
8'd154 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'h0000;
tsw <= addrs4+adcyccnt[15:8];
cntw <= 24 'h000000;
next <= 8'd155;
end
8'd155 : if ( cntw == 24 'd2 ) begin //
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd156;
end
8'd156 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd157;
end
8'd157 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd158;
end
8'd158 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h30;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
// c_cyc_count1<=16'h0000;
// storecnt<=8'b00000000;
//next <= 8'd159;
next <= 8'd159;//162 12/10 159 12/26
end
8'd159 : if ( cntw == 24 'd21 ) begin//12/14 70 12/26 70 12/30
if(RB == 1'b0)begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
cntw <= 24 'h000000;
next<=8'd158;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0; //0 12/10
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
// c_cyc_count1<=16'h0000;
// storecnt<=8'b00000000;
next <= 8'd162; //160
end
end
8'd160 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd161;
end
8'd161:if(cntw==24'd1)begin
if(RB == 1'b0)begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b0;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd161;
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd162;
end
end
8'd162:if(cntw==24'd5)begin //2019/11/17 'd5 d4 12/15 d5 12/24 d4だと05hでNG
// if(r_cyc_count1 < 16'h0003)begin
// if( c_cyc_count1 < caddrs1 || c_cyc_count1 == caddrs1)begin ///<=1
if( w_cyc_count1 < caddrs1 || w_cyc_count1 == caddrs1)begin ///<=1
// if(din != wdatain)begin
//////////////////////////////////
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din[7:0]};
// storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;//d0 12/12 12/15
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd163;
// end else if (c_cyc_count1 > caddrs1)begin //+1
end else if (w_cyc_count1 > caddrs1)begin //+1
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;//1//11/28
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
adcyccnt <= adcyccnt +1;
next <=8'd166; //d254 12/26 165
end
// end else begin
/* cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd163;
// end else if (r_cyc_count1 ==16'h0003)begin
end
end*/
end
8'd163:if(cntw==24'd4)begin //d1 12/15
// if(din != wdatain)begin
// CCERR <= 1'b0;
// ram[storecnt]<={addrp4,addrp3,addrp2[3:0],addrp1,din};
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din};
// storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd164;
/* end else begin
CCERR <= 1'b1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd164;
end*/
end
8'd164:if(cntw==24'd4) begin //12/14 d2 12/14 d4 d4 12/26
if(din != wdatain )begin
// if(din != c_cyc_count1[7:0] )begin
// if(din != w_cyc_count1[7:0] )begin
// if(DATA != wdatain)begin
CCERR <= 1'b0;
// ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+c_cyc_count1[11:8],addrs1+c_cyc_count1[7:0],din[7:0]};
ram[storecnt]<={addrs4+adcyccnt[15:8],addrs3+adcyccnt[7:0],addrs2[3:0]+w_cyc_count1[11:8],addrs1+w_cyc_count1[7:0],din[7:0]};
storecnt <= storecnt + 1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
// c_cyc_count1 <=c_cyc_count1 +1; //12/26
next <= 8'd165; //161 12/26 //162
end else begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
// c_cyc_count1 <=c_cyc_count1 +1; //12/26
next <= 8'd165; //161 12/26 //162
end
end
8'd165 : if ( cntw == 24 'd1 ) begin //
// c_cyc_count1 <=c_cyc_count1 +1;
w_cyc_count1 <=w_cyc_count1 +1;
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd161;
end
///////////////////////////////////////////conparecheck
////////////////////////compare check read status compare check concluding////////////////////////////////////////////////////////////////////////////
8'd166 : if ( cntw == 24 'd3 ) begin //
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd167;
end
8'd167 : if ( cntw == 24 'd1 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd168;
end
8'd168 : if ( cntw == 24 'd4 ) begin
cle <= 1'b1;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h70;
// tsw <= 8 'h5f; //movement check
cntw <= 24 'h000000;
next <= 8'd169;
end
8'd169 : if ( cntw == 24 'd2 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
// tsw <= 8 'hzz;//1210
tsw <= 8'h0000;
cntw <= 24 'h000000;
next <= 8'd170;
end
8'd170 : if ( cntw == 24 'd6 ) begin //disp_clear
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b0;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd171;
end
8'd171 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b1;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd172;
end
8'd172 : if ( cntw == 24 'd2 ) begin //entrymode_on
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;
wp <= 1'b1;
tsw <= 8 'hzz;
cntw <= 24 'h000000;
next <= 8'd173;
end
8'd173 : if ( cntw == 24 'd21 ) begin //21 12/16
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b0;
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd174;
end
8'd174 : if ( cntw == 24 'd4 ) begin
cle <= 1'b0;
cen <= 1'b0;
wen <= 1'b1;
ale <= 1'b0;
ren <= 1'b1;// read trigger 0Byte
wp <= 1'b1;
tsw <= 8 'h0000;
cntw <= 24 'h000000;
next <= 8'd175;//254 12/10
end
8'd175:if(cntw ==24'd2)begin //12/10
if(din ==8'h80||din==8'hc0)begin
next <= 8'd173; //d172 12/26
end else if(din ==8'he0)begin
next <=8'd254;
end
end
endcase
//end
end
end
//assign WP =wp;
assign WP =1'b1;
assign CLE = cle;
assign CE = cen;
assign WE = wen;
assign ALE =ale;
assign RE = ren;
//assign TSW=tsw;
//assign TSW = dataout;
assign ADCYCCNT =~adcyccnt;
assign EN = ~WE | ~RE ;
assign sEN = ~WE | ~RE;
assign W_CYC_COUNT1 =w_cyc_count1;
assign INSTATUS = instatus;
endmodule
"2-2.ソースコード下位層1(source code underlayer)" †
/* LCD_module_4bit */
module lcd_sc1602_06_4b_01( CLK,SHIFT_CLK, RST, CUR,rw ,rs ,en ,db,DATA,addrs1,addrs2,addrs3,addrs4,wdatain,EN,INSTATUS);
input CLK, RST ;
input[3:0] CUR;
//input[15:0] DATA;
input[7:0] DATA;
input[7:0] addrs1;
input[7:0] addrs2;
input[7:0] addrs3;
input[7:0] addrs4;
input[7:0] wdatain;
input[3:0] INSTATUS;
input EN;
output rw, rs ,SHIFT_CLK;
output en;
output [7:0] db;
reg [23:0] cntw;
reg [9:0] next;
reg rs_r;
reg en_r;
reg rw_r;
reg [7:0] tsw;
//reg[7:0] character_hex1,character_hex2,character_hex3,character_hex4;
//reg[127:0] mode_lcd_disp;
reg[31:0] sec_cnt1;
reg toggle_flag1;
reg sec1_flag1;
reg[31:0] sec_cnt2;
reg toggle_flag2;
reg sec1_flag2;
/*
reg[7:0] addrs1;
reg[7:0] addrs2;
reg[7:0] addrs3;
reg[7:0] addrs4;
*/
reg[11:0] caddrs1;
reg[15:0] chara_addrs1;
reg[15:0] chara_addrs2;
reg[15:0] chara_addrs3;
reg[15:0] chara_addrs4;
reg[15:0] chara_datain;
reg[15:0] chara_data1;
reg[127:0] mode_lcd_disp ;
initial begin
sec_cnt1=32'h00000000;
toggle_flag1 =1'b0;
sec1_flag1 =1'b0;
sec_cnt2=32'h00000000;
toggle_flag2 =1'b0;
sec1_flag2 =1'b0;
cntw =24'h000000;
next = 10'b0000000000;
tsw = 8'b00000000;
rs_r = 1'b0;
rw_r = 1'b0;
en_r = 1'b0;
//CUR=4'b0000;
//COUNTER_OUT=4'b1111;
// addrs1=8'h11;
// addrs2=8'h22;
// addrs3=8'h33;
// addrs4=8'h44;
//caddrs1=12'b101010101010;
end
//parameter F50M0000_cnt1=32'h000001f4;//10/30動作 10usec
parameter F50M0000_cnt1=32'h00000032;
// parameter F50M0000_cnt1=32'h00000032;
// parameter F50M0000_cnt1=32'h00000004;
parameter F50M0000_cnt2=32'h00000002;
always@(posedge CLK)
begin
if(sec_cnt1 == F50M0000_cnt1) begin
// if(sec_cnt1 == 32'h00000004) begin
sec_cnt1 <= 32'h00000000 ; //counter counting up to the parameter
sec1_flag1 <= 1'b1;
end else begin
sec_cnt1 <= sec_cnt1 + 1 ;
sec1_flag1 <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag1 == 1'b1 )begin
toggle_flag1 <= !toggle_flag1 ;
end
end
assign SHIFT_CLK =!toggle_flag1;
always@(posedge CLK)
begin
if(sec_cnt2 == F50M0000_cnt2) begin
// if(sec_cnt1 == 32'h00000004) begin
sec_cnt2 <= 32'h00000000 ; //counter counting up to the parameter
sec1_flag2 <= 1'b1;
end else begin
sec_cnt2 <= sec_cnt2 + 1 ;
sec1_flag2 <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag2 == 1'b1 )begin
toggle_flag2 <= !toggle_flag2 ;
end
end
always@(negedge RST or posedge toggle_flag2 ) //or posedge EN)
//always@(negedge RST or posedge SHIFT_CLK) //10/31
// always@(negedge RST or posedge CLK ) //or posedge EN)
begin if(RST ==1'b0)begin
//chara_addrs1 <=16'h3031;
//chara_addrs2 <=16'h3032;
//chara_addrs3 <=16'h3033;
//chara_addrs4 <=16'h3034;
//chara_data1 <=16'h3435;
//end else begin
//end else if(EN==1'b1)begin
end else begin
case(addrs1[3:0])
4'b0000 : chara_addrs1[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs1[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs1[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs1[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs1[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs1[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs1[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs1[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs1[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs1[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs1[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs1[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs1[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs1[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs1[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs1[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs1[7:0]<= 8'h31;
endcase
case(addrs1[7:4])
4'b0000 : chara_addrs1[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs1[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs1[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs1[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs1[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs1[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs1[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs1[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs1[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs1[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs1[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs1[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs1[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs1[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs1[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs1[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs1[15:8]<= 8'h32;
endcase
case(addrs2[3:0])
4'b0000 : chara_addrs2[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs2[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs2[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs2[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs2[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs2[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs2[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs2[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs2[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs2[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs2[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs2[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs2[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs2[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs2[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs2[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs2[7:0] <= 8'h33;
endcase
case(addrs2[7:4])
4'b0000 : chara_addrs2[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs2[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs2[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs2[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs2[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs2[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs2[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs2[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs2[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs2[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs2[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs2[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs2[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs2[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs2[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs2[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs2[15:8] <= 8'h34;
endcase
case(addrs3[3:0])
4'b0000 : chara_addrs3[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs3[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs3[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs3[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs3[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs3[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs3[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs3[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs3[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs3[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs3[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs3[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs3[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs3[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs3[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs3[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs3[7:0] <= 8'h35;
endcase
case(addrs3[7:4])
4'b0000 : chara_addrs3[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs3[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs3[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs3[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs3[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs3[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs3[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs3[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs3[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs3[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs3[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs3[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs3[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs3[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs3[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs3[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs3[15:8] <= 8'h36;
endcase
case(addrs4[3:0])
4'b0000 : chara_addrs4[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs4[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs4[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs4[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs4[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs4[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs4[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs4[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs4[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs4[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs4[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs4[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs4[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs4[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs4[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs4[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs4[7:0] <= 8'h36;
endcase
case(addrs4[7:4])
4'b0000 : chara_addrs4[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs4[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs4[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs4[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs4[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs4[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs4[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs4[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs4[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs4[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs4[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs4[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs4[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs4[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs4[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs4[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs4[15:8] <= 8'h37;
endcase
case(wdatain[3:0])
4'b0000 : chara_datain[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_datain[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_datain[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_datain[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_datain[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_datain[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_datain[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_datain[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_datain[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_datain[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_datain[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_datain[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_datain[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_datain[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_datain[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_datain[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_datain[7:0] <= 8'h36;
endcase
case(wdatain[7:4])
4'b0000 : chara_datain[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_datain[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_datain[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_datain[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_datain[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_datain[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_datain[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_datain[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_datain[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_datain[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_datain[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_datain[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_datain[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_datain[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_datain[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_datain[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_datain[15:8] <= 8'h37;
endcase
// default: chara_addrs4 <= 8'b00000110;
//endcase
end
end
// always@(negedge RST or posedge SHIFT_CLK) //10/31
always@(negedge RST or posedge CLK or posedge EN)
//begin if(RST ==1'b0)begin
//chara_addrs1 <=16'h3031;
//chara_addrs2 <=16'h3032;
//chara_addrs3 <=16'h3033;
//chara_addrs4 <=16'h3034;
//chara_data1 <=16'h3435;
//end else begin
//end else
if(EN==1'b1)begin
//end else begin 11/1
/*
case(addrs1[3:0])
4'b0000 : chara_addrs1[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs1[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs1[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs1[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs1[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs1[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs1[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs1[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs1[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs1[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs1[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs1[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs1[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs1[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs1[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs1[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs1[7:0]<= 8'h31;
endcase
case(addrs1[7:4])
4'b0000 : chara_addrs1[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs1[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs1[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs1[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs1[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs1[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs1[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs1[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs1[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs1[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs1[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs1[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs1[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs1[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs1[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs1[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs1[15:8]<= 8'h32;
endcase
case(addrs2[3:0])
4'b0000 : chara_addrs2[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs2[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs2[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs2[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs2[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs2[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs2[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs2[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs2[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs2[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs2[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs2[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs2[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs2[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs2[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs2[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs2[7:0] <= 8'h33;
endcase
case(addrs2[7:4])
4'b0000 : chara_addrs2[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs2[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs2[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs2[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs2[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs2[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs2[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs2[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs2[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs2[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs2[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs2[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs2[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs2[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs2[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs2[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs2[15:8] <= 8'h34;
endcase
case(addrs3[3:0])
4'b0000 : chara_addrs3[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs3[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs3[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs3[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs3[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs3[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs3[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs3[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs3[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs3[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs3[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs3[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs3[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs3[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs3[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs3[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs3[7:0] <= 8'h35;
endcase
case(addrs3[7:4])
4'b0000 : chara_addrs3[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs3[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs3[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs3[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs3[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs3[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs3[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs3[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs3[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs3[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs3[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs3[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs3[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs3[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs3[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs3[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs3[15:8] <= 8'h36;
endcase
case(addrs4[3:0])
4'b0000 : chara_addrs4[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs4[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs4[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs4[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs4[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs4[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs4[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs4[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs4[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs4[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs4[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs4[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs4[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs4[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs4[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs4[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs4[7:0] <= 8'h36;
endcase
case(addrs4[7:4])
4'b0000 : chara_addrs4[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs4[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs4[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs4[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs4[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs4[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs4[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs4[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs4[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs4[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs4[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs4[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs4[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs4[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs4[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs4[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs4[15:8] <= 8'h37;
endcase
*/
case(DATA[3:0])
4'b0000 : chara_data1[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_data1[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_data1[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_data1[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_data1[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_data1[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_data1[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_data1[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_data1[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_data1[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_data1[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_data1[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_data1[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_data1[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_data1[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_data1[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_data1[7:0] <= 8'h36;
endcase
case(DATA[7:4])
4'b0000 : chara_data1[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_data1[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_data1[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_data1[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_data1[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_data1[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_data1[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_data1[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_data1[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_data1[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_data1[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_data1[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_data1[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_data1[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_data1[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_data1[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_data1[15:8] <= 8'h37;
endcase
// default: chara_addrs4 <= 8'b00000110;
//endcase
//end
end
// parameter NORMAL = 4'b0000, READID = 4'b0001, READSTATUS = 4'b0010, READPAGE = 4'b0011 ,ERASEBLOCK = 4'b0100, PROGRAMPAGE = 4'b0101,READPARAMPAGE =4'b0110,READUNIID=4'b0111,COMPARECHECK=4'b1000;
// parameter AdSelStart=4'b1001,AdSelEnd=4'b1010,Adcycl=4'b1011,DataInput=4'b1100,Load=4'b1101,ErsPrgCom=4'b1110;
always@(posedge SHIFT_CLK )begin
// always@(posedge CLK or posedge sw2)begin
//read 0x03,0x0b,0x3b,0x6b,0xbb,0xeb,0x9f,0x90
if(CUR == 4'h0)begin
mode_lcd_disp <=128'h4e6f726d616c20202020202030783030 ;//display "Normal 0x00"
end else if(CUR == 4'h1)begin
mode_lcd_disp <=128'h52656164204944202020202030783031 ;//display "Read ID 0x01"
end else if(CUR == 4'h2)begin
mode_lcd_disp <=128'h52656164205354415455532030783032 ;//display "Read STATUS 0x02"
end else if(CUR == 4'h3)begin
mode_lcd_disp <=128'h52656164205041474520202030783033 ;//display "Read PAGE 0x03"
end else if(CUR == 4'h4)begin
mode_lcd_disp <=128'h455241534520424c4f434b2030783034 ;//display "ERASE BLOCK 0x04"
end else if(CUR == 4'h5)begin
mode_lcd_disp <=128'h50726f6772616d506167652030783035 ;//display "PROGRAMPAGE 0x05"
end else if(CUR == 4'h6)begin
mode_lcd_disp <=128'h52656164506172616d50202030783036 ;//display "ReadParamP 0x06"
end else if(CUR == 4'h7)begin
mode_lcd_disp <=128'h52656164556e69494420202030783037 ;//display "ReadUNIID 0x07"
end else if(CUR == 4'h8)begin
mode_lcd_disp <=128'h434f4d5020434845434b202030783038 ;//display "COMPARECHECK 0x08"
end else if(CUR == 4'h9)begin
mode_lcd_disp <=128'h416453656c2053746172742030783039 ;//display "AdSel Start 0x09"
end else if(CUR == 4'ha)begin
mode_lcd_disp <=128'h416453656c20456e6420202030783061 ;//display "AdSel End 0x0a"
end else if(CUR == 4'hb)begin
mode_lcd_disp <=128'h41646379636c20202020202030783062 ;//display "Adcycl 0x0b"
end else if(CUR == 4'hc)begin
mode_lcd_disp <=128'h4461746120496e707574202030783063 ;//display "Data Input 0x0c"
end else if(CUR == 4'hd)begin
mode_lcd_disp <=128'h4c6f6164202020202020202030783064 ;//display "Load 0x0d"
end else if(CUR == 4'he)begin
if(INSTATUS == 4'b0001)begin
mode_lcd_disp <=128'h4572737e202020202020202030783065 ;//display "Ers-> 0x0e"
end else if(INSTATUS ==4'b0010)begin
mode_lcd_disp <=128'h5072677e202020202020202030783065 ;//display "Prg-> 0x0e"
end else if(INSTATUS == 4'b0100)begin
mode_lcd_disp <=128'h436f6d7e202020202020202030783065 ;//display "Com-> 0x0e"
end else begin
mode_lcd_disp <=128'h457273507267436f6d20202030783065 ;//display "ErsPrgCom 0x0e"
end
end else begin
mode_lcd_disp <=128'h45727220436865636b20496e20202020 ;//display "Err Check Input "
end
end
always @( posedge SHIFT_CLK ) begin
//always @( posedge SHIFT_CLK or posedge EN) begin //10/31
//always @( negedge RST or posedge CLK ) begin
if ( RST==1 'b0 ) begin
rs_r <= 1'b0;
rw_r <= 1'b0;
en_r <= 1'b0;
// tsw <= 8 'h00;
tsw <= 8 'h20;//11/1
cntw <= 24 'h000000;
next <= 10'd0;
end else if (cntw == 24 'h0cb735)begin
// end else if (cntw == 24 'h000ccc)begin
cntw <= 24 'h000000;
end else begin
cntw <= cntw + 1'b1;
//delya 50msec rs=0
case (next)
10'd0 : if ( cntw == 24 'd50000 ) begin // all_0 & 50ms_wait rs=0 command 50Mhz count 1 = 1usec 50000 = 50msec
rs_r <= 1'b0;
rw_r <= 1'b0;
en_r <= 1'b0;
tsw <= 8'h0;
cntw <= 24'h000000;
next <= 10'd1;
end
//3h 8bitmode 1
10'd1 : if ( cntw == 24 'd1 ) begin //8bit_mode rs=0
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 10'd2;
end
10'd2 : if ( cntw == 24 'd1 ) begin //en_hold_1us rs=0
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd3;
end
//3h 8bitmode 2
10'd3 : if ( cntw == 24 'd5000 ) begin //8bit_mode & 5ms_wait rs=0
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 10'd4;
end
10'd4 : if ( cntw == 24 'd1 ) begin // rs=0
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd5;
end
//3h 8bitmode 3
10'd5 : if ( cntw == 24 'd1000 ) begin //8bit_mode & 1ms_wait rs=0
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 10'd6;
end
10'd6 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd7;
end
//4bit mode 20h half byte only
10'd7 : if ( cntw == 24 'd5000 ) begin //Function set("4"bit_mode & 2disp) & 5ms_wait rs=0
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd8;
end
10'd8 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd900;
end
//2gyouhyouji 28h //8bitmode 38h
10'd900 : if ( cntw == 24 'd5000 ) begin //Function set("4"bit_mode & 2disp) & 5ms_wait
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd901;
end
10'd901 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd902;
end
10'd902 : if ( cntw == 24 'd5000 ) begin //Function set("4"bit_mode & 2disp) & 5ms_wait
en_r <= 1'b1;
tsw <= 8'h80;
cntw <= 24'h00;
next <= 10'd903;
end
10'd903 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd904;
end
//disp on off/ 08h
10'd904 : if ( cntw == 24 'd50 ) begin //disp_on
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd905;
end
10'd905 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd906;
end
10'd906 : if ( cntw == 24 'd50 ) begin //disp_on
en_r <= 1'b1;
tsw <= 8'hc0;//E0
cntw <= 24'h00;
next <= 10'd907;
end
10'd907 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd908;
end
10'd908 : if ( cntw == 24 'd50 ) begin //disp_clear
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd909;
end
10'd909 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd910;
end
10'd910 : if ( cntw == 24 'd50 ) begin //disp_clear
en_r <= 1'b1;
tsw <= 8'h10;//E0
cntw <= 24'h00;
next <= 10'd911;
end
10'd911 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd912;
end
//entrymode 04h
10'd912 : if ( cntw == 24 'd16000 ) begin //entrymode_on
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd913;
end
10'd913 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd914;
end
10'd914 : if ( cntw == 24 'd50 ) begin //entrymode_on
en_r <= 1'b1;
tsw <= 8'h60; //60
cntw <= 24'h00;
next <= 10'd915;
end
10'd915 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd916;
end
//display on 06h
10'd916 : if ( cntw == 24 'd15000 ) begin //address指定
en_r <= 1'b1;
tsw <= 8'h80;
cntw <= 24'h00;
next <= 10'd917;
end
10'd917 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd918;
end
10'd918 : if ( cntw == 24 'd50 ) begin //
en_r <= 1'b1;
tsw <= 8'h00;//F0
cntw <= 24'h00;
next <= 10'd919;
end
10'd919 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd22;
end
//rs ->1 command end
10'd22 : if ( cntw == 24 'd50 ) begin //rs_enb
rs_r <= 1'b1;
cntw <= 24'h00;
next <= 10'd23;
end
//character out 1gyou 1moji MSB->LSB
10'd23 : if ( cntw == 24 'd50 ) begin //character_out w
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[127:124];
cntw <= 24'h00;
next <= 10'd24;
end
10'd24 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd25;
end
10'd25 : if ( cntw == 24 'd50 ) begin //character_out w
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[123:120];
cntw <= 24'h00;
next <= 10'd26;
end
10'd26 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd27;
end
//1-2
10'd27 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[119:116];
cntw <= 24'h00;
next <= 10'd28;
end
10'd28 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd29;
end
10'd29 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[115:112];
cntw <= 24'h00;
next <= 10'd30;
end
10'd30 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd31;
end
//1-3
10'd31 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[111:108];
cntw <= 24'h00;
next <= 10'd32;
end
10'd32 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd33;
end
10'd33 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[107:104];
cntw <= 24'h00;
next <= 10'd34;
end
10'd34 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd35;
end
//1-4
10'd35 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[103:100];
cntw <= 24'h00;
next <= 10'd36;
end
10'd36 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd37;
end
10'd37 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[99:96];
cntw <= 24'h00;
next <= 10'd38;
end
10'd38 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd39;
end
//1-5
10'd39 : if ( cntw == 24 'd50 ) begin //character_out
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[95:92];
cntw <= 24'h00;
next <= 10'd40;
end
10'd40 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd41;
end
10'd41 : if ( cntw == 24 'd50 ) begin //character_out
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[91:88];
cntw <= 24'h00;
next <= 10'd42;
end
10'd42 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd43;
end
//1-6
10'd43 : if ( cntw == 24 'd50 ) begin //character_out c
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[87:84];
cntw <= 24'h00;
next <= 10'd44;
end
10'd44 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd45;
end
10'd45 : if ( cntw == 24 'd50 ) begin //character_out c
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[83:80];
cntw <= 24'h00;
next <= 10'd46;
end
10'd46 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd48;
end
//1-7
10'd48 : if ( cntw == 24 'd50 ) begin //character_out o
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[79:76];
cntw <= 24'h00;
next <= 10'd49;
end
10'd49 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd50;
end
10'd50 : if ( cntw == 24 'd50 ) begin //character_out o
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[75:72];
cntw <= 24'h00;
next <= 10'd51;
end
10'd51 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 810'd52;
end
//1-8
10'd52 : if ( cntw == 24 'd50 ) begin //character_out u
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[71:68];
cntw <= 24'h00;
next <= 10'd53;
end
10'd53 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd54;
end
10'd54 : if ( cntw == 24 'd50 ) begin //character_out u
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[67:64];
cntw <= 24'h00;
next <= 10'd55;
end
10'd55 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd56;
end
//1-9
10'd56 : if ( cntw == 24 'd50 ) begin //character_out n
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[63:60];
cntw <= 24'h00;
next <= 10'd57;
end
10'd57 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd58;
end
10'd58 : if ( cntw == 24 'd50 ) begin //character_out n
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[59:56];
cntw <= 24'h00;
next <= 10'd60;
end
10'd60 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd61;
end
//1-10
10'd61 : if ( cntw == 24 'd50 ) begin //character_out t
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[55:52];
cntw <= 24'h00;
next <= 10'd62;
end
10'd62 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd63;
end
10'd63 : if ( cntw == 24 'd50 ) begin //character_out t
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[51:48];
cntw <= 24'h00;
next <= 10'd64;
end
10'd64 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd65;
end
//1-11
10'd65 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[47:44];
cntw <= 24'h00;
next <= 10'd66;
end
10'd66 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd67;
end
10'd67 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[43:40];
cntw <= 24'h00;
next <= 10'd68;
end
10'd68 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd70;
end
//1-12
10'd70 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[39:36];
cntw <= 24'h00;
next <= 10'd71;
end
10'd71 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd72;
end
10'd72 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[35:32];
cntw <= 24'h00;
next <= 10'd73;
end
10'd73 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd74;
end
//1-13
10'd74 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[31:28];
cntw <= 24'h00;
next <= 10'd75;
end
10'd75 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd76;
end
10'd76 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[27:24];
cntw <= 24'h00;
next <= 10'd77;
end
10'd77 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd78;
end
//1-14
10'd78 : if ( cntw == 24 'd50 ) begin //character_out 6
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[23:20];
cntw <= 24'h00;
next <= 10'd79;
end
10'd79 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd80;
end
10'd80 : if ( cntw == 24 'd50 ) begin //character_out 6
en_r <= 1'b1;
tsw[7:4] <= mode_lcd_disp[19:16];
cntw <= 24'h00;
next <= 10'd81;
end
10'd81 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd82;
end
//1-15
10'd82 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
// tsw <= mode_lcd_disp[15:8];
tsw[7:4]<=chara_datain[15:12];
cntw <= 24'h00;
next <= 10'd83;
end
10'd83 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd84;
end
10'd84 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
// tsw <= mode_lcd_disp[15:8];
tsw[7:4]<=chara_datain[11:8];
cntw <= 24'h00;
next <= 10'd85;
end
10'd85 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd86;
end
//1-16
10'd86 : if ( cntw == 24 'd50 ) begin //character_out 1
en_r <= 1'b1;
// tsw <= mode_lcd_disp[7:0];
tsw[7:4]<=chara_datain[7:4];
cntw <= 24'h00;
next <= 10'd87;
end
10'd87 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// rs_r <= 1'b0;
next <= 10'd88;
end
10'd88 : if ( cntw == 24 'd50 ) begin //character_out 1
en_r <= 1'b1;
// tsw <= mode_lcd_disp[7:0];
tsw[7:4]<=chara_datain[3:0];
cntw <= 24'h00;
next <= 10'd89;
end
10'd89 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
next <= 10'd90;//90
end
//2nd column start rs_r=0 command
10'd90 : if ( cntw == 24 'd1500 ) begin ////////////////////character_out 2column selected 0x40 1rst 11/6 500->1500
en_r <= 1'b1;
tsw <= 8'hc0;
cntw <= 24'h00;
next <= 10'd91;
end
10'd91 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// rs_r <= 1'b0; //1
next <= 10'd92;
end
10'd92 : if ( cntw == 24 'd500 ) begin ////////////////////character_out 2column selected 0x40 1rst
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd93;
end
10'd93 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b1;
next <= 10'd94;
end
//2-1
10'd94 : if ( cntw == 24 'd50 ) begin //character_out A 0x41
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h40;
cntw <= 24'h00;
next <= 10'd95;
end
10'd95 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd96;
end
10'd96 : if ( cntw == 24 'd50 ) begin //character_out A
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h10;
cntw <= 24'h00;
next <= 10'd97;
end
10'd97 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd98;
end
//2-2
10'd98 : if ( cntw == 24 'd50 ) begin //character_out d 0x64
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h60;
cntw <= 24'h00;
next <= 10'd99;
end
10'd99 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd100;
end
10'd100 : if ( cntw == 24 'd50 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h40;
cntw <= 24'h00;
next <= 10'd101;
end
10'd101 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd102;
end
//2-3 72h r
10'd102 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h70;
cntw <= 24'h00;
next <= 10'd103;
end
10'd103 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd104;
end
10'd104 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd105;
end
10'd105 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd106;
end
//2-4
10'd106 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd107;
end
10'd107 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd108;
end
10'd108 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd109;
end
10'd109 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd110;
end
//2-5
10'd110 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs4[15:12];
cntw <= 24'h00;
next <= 10'd111;
end
10'd111 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd112;
end
10'd112 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs4[11:8];
cntw <= 24'h00;
next <= 10'd113;
end
10'd113 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd114;
end
//2-6
10'd114 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs4[7:4];
cntw <= 24'h00;
next <=10'd115;
end
10'd115 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd116;
end
10'd116 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs4[3:0];
cntw <= 24'h00;
next <=10'd117;
end
10'd117 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd118;
end
//2-7
10'd118 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs3[15:12];
cntw <= 24'h00;
next <=10'd119;
end
10'd119 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd120;
end
10'd120 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs3[11:8];
cntw <= 24'h00;
next <=10'd121;
end
10'd121 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd122;
end
//2-8
10'd122 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs3[7:4];
cntw <= 24'h00;
next <= 10'd123;
end
10'd123 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd124;
end
10'd124 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs3[3:0];
cntw <= 24'h00;
next <= 10'd125;
end
10'd125 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd126;
end
//2-9
10'd126 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs2[7:4];
cntw <= 24'h00;
next <= 10'd127;
end
10'd127 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd128;
end
10'd128 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs2[3:0];
cntw <= 24'h00;
next <= 10'd129;
end
10'd129 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd130;
end
//2-10
10'd130 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw[7:4] <= chara_addrs1[15:12];
cntw <= 24'h00;
next <= 10'd138;
end
10'd138 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd139;
end
10'd139 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw[7:4] <= chara_addrs1[11:8];
cntw <= 24'h00;
next <= 10'd140;
end
10'd140 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd141;
end
//2-11
10'd141 : if ( cntw == 24 'd50) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw[7:4] <= chara_addrs1[7:4];
cntw <= 24'h00;
next <= 10'd142;
end
10'd142 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd143;
end
10'd143 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw[7:4] <= chara_addrs1[3:0];
cntw <= 24'h00;
next <= 10'd144;
end
10'd144 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd145;
end
//2-12
10'd145 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd146;
end
10'd146 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd147;
end
10'd147 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd148;
end
10'd148 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd149;
end
//2-13
10'd149 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h30;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 10'd150;
end
10'd150 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd151;
end
10'd151 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h00;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 10'd152;
end
10'd152 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd153;
end
//2-14
10'd153 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h70;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 10'd154;
end
10'd154 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd155;
end
10'd155 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h80;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 10'd156;
end
10'd156 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd157;
end
//2-15
10'd157 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw[7:4] <= chara_data1[15:12];
cntw <= 24'h00;
next <= 10'd159;
end
10'd159 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd160;
end
10'd160 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw[7:4] <= chara_data1[11:8];
cntw <= 24'h00;
next <= 10'd161;
end
10'd161 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd162;
end
//2-16
10'd162 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw[7:4] <= chara_data1[7:4];
cntw <= 24'h00;
next <= 10'd163;
end
10'd163 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd164;
// next <= 8'd94;
end
10'd164 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw[7:4] <= chara_data1[3:0];
cntw <= 24'h00;
next <= 10'd165;
end
10'd165 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd166;
// next <= 10'd908;
end
/* 8'd82 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'h83; //8'hxx
end
*/
//2 end
10'd166 : if ( cntw == 24 'd50 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
// next <= 8'd84;
next <= 10'd167; //10/28
end
10'd167 : if ( cntw == 24 'd1500 ) begin //character_out 2column selected 0x40 update
en_r <= 1'b1;
tsw <= 8'hc0;
// tsw <= 8'hcc;
cntw <= 24'h00;
next <= 10'd168;
end
10'd168 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// rs_r <= 1'b1;
next <= 10'd169;
end
10'd169 : if ( cntw == 24 'd500 ) begin //character_out 2column selected 0x40 update
en_r <= 1'b1;
tsw <= 8'h00;
// tsw <= 8'hcc;
cntw <= 24'h00;
next <= 10'd170;
end
10'd170 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b1;
next <= 10'd171;
end
//2 2-1
10'd171 : if ( cntw == 24 'd50 ) begin //character_out A
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h40;
cntw <= 24'h00;
next <= 10'd172;
end
10'd172 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd173;
end
10'd173 : if ( cntw == 24 'd50 ) begin //character_out A
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h10;
cntw <= 24'h00;
next <= 10'd174;
end
10'd174 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd175;
end
//2 2-2
10'd175 : if ( cntw == 24 'd50 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h60;
cntw <= 24'h00;
next <= 10'd176;
end
10'd176 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd177;
end
10'd177 : if ( cntw == 24 'd50 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h40;
cntw <= 24'h00;
next <= 10'd178;
end
10'd178 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd179;
end
//2 2-3
10'd179 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h70;
cntw <= 24'h00;
next <= 10'd180;
end
10'd180 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd181;
end
10'd181 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd182;
end
10'd182 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd183;
end
//2 2-4
10'd183 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd185;
end
10'd185 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd186;
end
10'd186 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd187;
end
10'd187 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd188;
end
// 2-5
10'd188 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs4[15:12];
cntw <= 24'h00;
next <= 10'd189;
end
10'd189 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd190;
end
10'd190 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs4[11:8];
cntw <= 24'h00;
next <= 10'd191;
end
10'd191 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd192;
end
//2 2-6
10'd192 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs4[7:4];
cntw <= 24'h00;
next <= 10'd193;
end
10'd193 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd194;
end
10'd194 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs4[3:0];
cntw <= 24'h00;
next <= 10'd195;
end
10'd195 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd196;
end
//2 2-7
10'd196 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs3[15:12];
cntw <= 24'h00;
next <= 10'd197;
end
10'd197 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd198;
end
10'd198 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs3[11:8];
cntw <= 24'h00;
next <= 10'd199;
end
10'd199 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd201;
end
//2 2-8
10'd201 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs3[7:4];
cntw <= 24'h00;
next <= 10'd202;
end
10'd202 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd203;
end
10'd203 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs3[3:0];
cntw <= 24'h00;
next <= 10'd204;
end
10'd204 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd205;
end
//2 2-9
10'd205 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs2[7:4];
cntw <= 24'h00;
next <= 10'd206;
end
10'd206 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd207;
end
10'd207 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrs2[3:0];
cntw <= 24'h00;
next <= 10'd208;
end
10'd208 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd209;
end
//2 /2-10
10'd209 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw[7:4] <= chara_addrs1[15:12];
cntw <= 24'h00;
next <= 10'd210;
end
10'd210 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd211;
end
10'd211 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw[7:4] <= chara_addrs1[11:8];
cntw <= 24'h00;
next <= 10'd212;
end
10'd212 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd213;
end
//2 2-11
10'd213 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw[7:4] <= chara_addrs1[7:4];
cntw <= 24'h00;
next <= 10'd214;
end
10'd214 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd215;
end
10'd215 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw[7:4] <= chara_addrs1[3:0];
cntw <= 24'h00;
next <= 10'd216;
end
10'd216 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd217;
end
//2 2-12
10'd217 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd218;
end
10'd218 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd219;
end
10'd219 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd220;
end
10'd220 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd221;
end
//2 2-13
10'd221 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h30;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 10'd222;
end
10'd222 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd223;
end
10'd223 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h00;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 10'd224;
end
10'd224 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd225;
end
//2 2-14 78h
10'd225 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h70;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 10'd226;
end
10'd226 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd227;
end
10'd227 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h80;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 10'd228;
end
10'd228 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd229;
end
//2 2-15
10'd229 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw[7:4] <= chara_data1[15:12];
cntw <= 24'h00;
next <= 10'd230;
end
10'd230 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd231;
end
10'd231 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw[7:4] <= chara_data1[11:8];
cntw <= 24'h00;
next <= 10'd232;
end
10'd232 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd233;
end
//2 2-16
10'd233 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw[7:4] <= chara_data1[7:4];
cntw <= 24'h00;
next <= 10'd234;
end
10'd234 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// rs_r<=1'b0;//10/31
next <= 10'd235;
// next <= 8'd94;
end
10'd235 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw[7:4] <= chara_data1[3:0];
cntw <= 24'h00;
next <= 10'd236;
end
10'd236 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r<=1'b0;//10/31
next <= 10'd237;
// next <= 8'd94;
end
/* 8'd82 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'h83; //8'hxx
end
*/
/*8'd118 : if ( cntw == 24 'd500 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
// next <= 8'd84;
next <= 8'd119; //10/28
end */
10'd237 : if ( cntw == 24 'd1500 ) begin //character_out 1column selected 0x00
en_r <= 1'b1;
// tsw <= 8'hc0;
tsw <= 8'h80;
cntw <= 24'h00;
next <= 10'd238;
end
10'd238 : if ( cntw == 24 'd1 ) begin
rw_r <= 1'b0;
// rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd239;
end
10'd239 : if ( cntw == 24 'd50 ) begin //character_out 1column selected 0x00
en_r <= 1'b1;
// tsw <= 8'hc0;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd240;
end
10'd240 : if ( cntw == 24 'd1 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd241;
end
10'd241:if(cntw==24'd1 )begin//&& CUR !=4'b1000)begin
next <= 10'd912;//83 22
//end else begin
// next <=8'd15;
end
endcase
end
end
/*
always @( posedge SHIFT_CLK ) begin
//always @( posedge SHIFT_CLK or posedge EN) begin //10/31
if ( RST==1 'b0 ) begin
rs_r <= 1'b0;
rw_r <= 1'b0;
en_r <= 1'b0;
// tsw <= 8 'h00;
tsw <= 8 'h20;//11/1
cntw <= 24 'h000000;
next <= 8'd0;
end else if (cntw == 24 'h0cb735)begin
// end else if (cntw == 24 'h000ccc)begin
cntw <= 24 'h000000;
end else begin
cntw <= cntw + 1'b1;
case (next)
8'd0 : if ( cntw == 24 'd50000 ) begin // all_0 & 50ms_wait
rs_r <= 1'b0;
rw_r <= 1'b0;
en_r <= 1'b0;
tsw <= 8'h0;
cntw <= 24'h000000;
next <= 8'd1;
end
8'd1 : if ( cntw == 24 'd1 ) begin //8bit_mode
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 8'd2;
end
8'd2 : if ( cntw == 24 'd1 ) begin //en_hold_1us
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd3;
end
8'd3 : if ( cntw == 24 'd5000 ) begin //8bit_mode & 5ms_wait
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 8'd4;
end
8'd4 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd5;
end
8'd5 : if ( cntw == 24 'd1000 ) begin //8bit_mode & 1ms_wait
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 8'd6;
end
8'd6 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd7;
end
8'd7 : if ( cntw == 24 'd5000 ) begin //Function set(8bit_mode & 2disp) & 5ms_wait
en_r <= 1'b1;
tsw <= 8'h38;
cntw <= 24'h00;
next <= 8'd8;
end
8'd8 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd9;
end
8'd9 : if ( cntw == 24 'd1000 ) begin //disp_clear
en_r <= 1'b1;
tsw <= 8'h01;
cntw <= 24'h00;
next <= 8'd10;
end
8'd10 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd11;
end
8'd11 : if ( cntw == 24 'd2000 ) begin //entrymode_on
en_r <= 1'b1;
tsw <= 8'h06;
cntw <= 24'h00;
next <= 8'd12;
end
8'd12 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd13;
end
8'd13 : if ( cntw == 24 'd1000 ) begin //disp_on & cursor_on & blink_on
en_r <= 1'b1;
tsw <= 8'h0F;
cntw <= 24'h00;
next <= 8'd14;
end
8'd14 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd15;
end
8'd15 : if ( cntw == 24 'd500 ) begin //rs_enb
rs_r <= 1'b1;
cntw <= 24'h00;
next <= 8'd16;
end
8'd16 : if ( cntw == 24 'd1 ) begin //character_out w
en_r <= 1'b1;
tsw <= mode_lcd_disp[127:120];
cntw <= 24'h00;
next <= 8'd17;
end
8'd17 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd18;
end
8'd18 : if ( cntw == 24 'd500 ) begin //character_out r
en_r <= 1'b1;
tsw <= mode_lcd_disp[119:112];
cntw <= 24'h00;
next <= 8'd19;
end
8'd19 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd20;
end
8'd20 : if ( cntw == 24 'd500 ) begin //character_out r
en_r <= 1'b1;
tsw <= mode_lcd_disp[111:104];
cntw <= 24'h00;
next <= 8'd21;
end
8'd21 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd22;
end
8'd22 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
tsw <= mode_lcd_disp[103:96];
cntw <= 24'h00;
next <= 8'd23;
end
8'd23 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd24;
end
8'd24 : if ( cntw == 24 'd500 ) begin //character_out
en_r <= 1'b1;
tsw <= mode_lcd_disp[95:88];
cntw <= 24'h00;
next <= 8'd25;
end
8'd25 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd26;
end
8'd26 : if ( cntw == 24 'd500 ) begin //character_out c
en_r <= 1'b1;
tsw <= mode_lcd_disp[87:80];
cntw <= 24'h00;
next <= 8'd27;
end
8'd27 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd28;
end
8'd28 : if ( cntw == 24 'd500 ) begin //character_out o
en_r <= 1'b1;
tsw <= mode_lcd_disp[79:72];
cntw <= 24'h00;
next <= 8'd29;
end
8'd29 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd30;
end
8'd30 : if ( cntw == 24 'd500 ) begin //character_out u
en_r <= 1'b1;
tsw <= mode_lcd_disp[71:64];
cntw <= 24'h00;
next <= 8'd31;
end
8'd31 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd32;
end
8'd32 : if ( cntw == 24 'd500 ) begin //character_out n
en_r <= 1'b1;
tsw <= mode_lcd_disp[63:56];
cntw <= 24'h00;
next <= 8'd33;
end
8'd33 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd34;
end
8'd34 : if ( cntw == 24 'd500 ) begin //character_out t
en_r <= 1'b1;
tsw <= mode_lcd_disp[55:48];
cntw <= 24'h00;
next <= 8'd35;
end
8'd35 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd36;
end
8'd36 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
tsw <= mode_lcd_disp[47:40];
cntw <= 24'h00;
next <= 8'd37;
end
8'd37 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd38;
end
8'd38 : if ( cntw == 24 'd500 ) begin //character_out x
en_r <= 1'b1;
tsw <= mode_lcd_disp[39:32];
cntw <= 24'h00;
next <= 8'd39;
end
8'd39 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd40;
end
8'd40 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
tsw <= mode_lcd_disp[31:24];
cntw <= 24'h00;
next <= 8'd41;
end
8'd41 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd42;
end
8'd42 : if ( cntw == 24 'd500 ) begin //character_out 6
en_r <= 1'b1;
tsw <= mode_lcd_disp[23:16];
cntw <= 24'h00;
next <= 8'd43;
end
8'd43 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd44;
end
8'd44 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
// tsw <= mode_lcd_disp[15:8];
tsw<=chara_datain[15:8];
cntw <= 24'h00;
next <= 8'd45;
end
8'd45 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd46;
end
8'd46 : if ( cntw == 24 'd500 ) begin //character_out 1
en_r <= 1'b1;
// tsw <= mode_lcd_disp[7:0];
tsw<=chara_datain[7:0];
cntw <= 24'h00;
next <= 8'd47;
end
8'd47 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
next <= 8'd48;
end
//2nd column start
8'd48 : if ( cntw == 24 'd500 ) begin ////////////////////character_out 2column selected 0x40 1rst
en_r <= 1'b1;
tsw <= 8'hc0;
cntw <= 24'h00;
next <= 8'd49;
end
8'd49 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b1;
next <= 8'd50;
end
8'd50 : if ( cntw == 24 'd500 ) begin //character_out A
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h41;
cntw <= 24'h00;
next <= 8'd51;
end
8'd51 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd52;
end
8'd52 : if ( cntw == 24 'd500 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h64;
cntw <= 24'h00;
next <= 8'd53;
end
8'd53 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd54;
end
8'd54 : if ( cntw == 24 'd500 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h72;
cntw <= 24'h00;
next <= 8'd55;
end
8'd55 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd56;
end
8'd56 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 8'd57;
end
8'd57 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd58;
end
8'd58 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs4[15:8];
cntw <= 24'h00;
next <= 8'd59;
end
8'd59 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd60;
end
8'd60 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs4[7:0];
cntw <= 24'h00;
next <= 8'd61;
end
8'd61 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd62;
end
8'd62 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs3[15:8];
cntw <= 24'h00;
next <= 8'd63;
end
8'd63 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd64;
end
8'd64 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs3[7:0];
cntw <= 24'h00;
next <= 8'd65;
end
8'd65 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd66;
end
8'd66 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs2[7:0];
cntw <= 24'h00;
next <= 8'd67;
end
8'd67 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd68;
end
8'd68 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw <= chara_addrs1[15:8];
cntw <= 24'h00;
next <= 8'd69;
end
8'd69 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd70;
end
8'd70 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw <= chara_addrs1[7:0];
cntw <= 24'h00;
next <= 8'd71;
end
8'd71 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd72;
end
8'd72 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 8'd73;
end
8'd73 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd74;
end
8'd74 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h30;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 8'd75;
end
8'd75 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd76;
end
8'd76 : if ( cntw == 24 'd500 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h78;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 8'd77;
end
8'd77 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd78;
end
8'd78 : if ( cntw == 24 'd500 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw <= chara_data1[15:8];
cntw <= 24'h00;
next <= 8'd79;
end
8'd79 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd80;
end
8'd80 : if ( cntw == 24 'd500 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw <= chara_data1[7:0];
cntw <= 24'h00;
next <= 8'd81;
end
8'd81 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd83;
// next <= 8'd94;
end
/* 8'd82 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'h83; //8'hxx
end
8'd83 : if ( cntw == 24 'd500 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
// next <= 8'd84;
next <= 8'd84; //10/28
end
8'd84 : if ( cntw == 24 'd500 ) begin //character_out 2column selected 0x40 update
en_r <= 1'b1;
tsw <= 8'hc0;
// tsw <= 8'hcc;
cntw <= 24'h00;
next <= 8'd85;
end
8'd85 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b1;
next <= 8'd86;
end
8'd86 : if ( cntw == 24 'd500 ) begin //character_out A
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h41;
cntw <= 24'h00;
next <= 8'd87;
end
8'd87 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd88;
end
8'd88 : if ( cntw == 24 'd500 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h64;
cntw <= 24'h00;
next <= 8'd89;
end
8'd89 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd90;
end
8'd90 : if ( cntw == 24 'd500 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h72;
cntw <= 24'h00;
next <= 8'd91;
end
8'd91 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd92;
end
8'd92 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 8'd93;
end
8'd93 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd94;
end
8'd94 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs4[15:8];
cntw <= 24'h00;
next <= 8'd95;
end
8'd95 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd96;
end
8'd96 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs4[7:0];
cntw <= 24'h00;
next <= 8'd97;
end
8'd97 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd98;
end
8'd98 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs3[15:8];
cntw <= 24'h00;
next <= 8'd99;
end
8'd99 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd100;
end
8'd100 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs3[7:0];
cntw <= 24'h00;
next <= 8'd101;
end
8'd101 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd102;
end
8'd102 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs2[7:0];
cntw <= 24'h00;
next <= 8'd103;
end
8'd103 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd104;
end
8'd104 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw <= chara_addrs1[15:8];
cntw <= 24'h00;
next <= 8'd105;
end
8'd105 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd106;
end
8'd106 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw <= chara_addrs1[7:0];
cntw <= 24'h00;
next <= 8'd107;
end
8'd107 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd108;
end
8'd108 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 8'd109;
end
8'd109 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd110;
end
8'd110 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h30;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 8'd111;
end
8'd111 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd112;
end
8'd112 : if ( cntw == 24 'd500 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h78;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 8'd113;
end
8'd113 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd114;
end
8'd114 : if ( cntw == 24 'd500 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw <= chara_data1[15:8];
cntw <= 24'h00;
next <= 8'd115;
end
8'd115 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd116;
end
8'd116 : if ( cntw == 24 'd500 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw <= chara_data1[7:0];
cntw <= 24'h00;
next <= 8'd117;
end
8'd117 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r<=1'b0;//10/31
next <= 8'd118;
// next <= 8'd94;
end
/* 8'd82 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'h83; //8'hxx
end
*/
/*8'd118 : if ( cntw == 24 'd500 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
// next <= 8'd84;
next <= 8'd119; //10/28
end
8'd118 : if ( cntw == 24 'd500 ) begin //character_out 1column selected 0x00
en_r <= 1'b1;
// tsw <= 8'hc0;
tsw <= 8'h80;
cntw <= 24'h00;
next <= 8'd119;
end
8'd119 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <=8'd120;
end
8'd120:if(cntw==24'd1 )begin//&& CUR !=4'b1000)begin
next <= 10'd15;//83 //15
//end else begin
// next <=8'd15;
end
endcase
end
end
*/
assign db = tsw;
assign rw = rw_r;
assign en = en_r;
assign rs = rs_r;
endmodule
"2-2.ソースコード下位層2(source code underlayer)" †
/* LCD_module_4bit */
module lcd_sc1602_06_4b_01ch01( CLK,SHIFT_CLK, RST, CUR,rw ,rs ,en ,db,DATA,addrs1,addrs2,addrs3,addrs4,wdatain,EN,erdata,,erdatanxt,loadcnt,loadcntnxt);
input CLK, RST ;
input[3:0] CUR;
input[7:0] DATA;
input[7:0] addrs1;
input[7:0] addrs2;
input[7:0] addrs3;
input[7:0] addrs4;
input[7:0] wdatain;
input[35:0] erdata;
input[35:0] erdatanxt;
input[7:0] loadcnt;
input[7:0] loadcntnxt;
input EN;
output rw, rs ,SHIFT_CLK;
output en;
output [7:0] db;
reg [23:0] cntw;
reg [9:0] next;
reg rs_r;
reg en_r;
reg rw_r;
reg [7:0] tsw;
//reg[7:0] character_hex1,character_hex2,character_hex3,character_hex4;
//reg[127:0] mode_lcd_disp;
reg[31:0] sec_cnt1;
reg toggle_flag1;
reg sec1_flag1;
reg[31:0] sec_cnt2;
reg toggle_flag2;
reg sec1_flag2;
/*
reg[7:0] addrs1;
reg[7:0] addrs2;
reg[7:0] addrs3;
reg[7:0] addrs4;
*/
reg[11:0] caddrs1;
reg[15:0] chara_addrs1;
reg[15:0] chara_addrs2;
reg[15:0] chara_addrs3;
reg[15:0] chara_addrs4;
reg[15:0] chara_datain;
reg[15:0] chara_data1;
reg[15:0] chara_addrt1;
reg[15:0] chara_addrt2;
reg[15:0] chara_addrt3;
reg[15:0] chara_addrt4;
reg[15:0] chara_dataint;
reg[15:0] chara_data2;
reg[127:0] mode_lcd_disp ;
initial begin
sec_cnt1=32'h00000000;
toggle_flag1 =1'b0;
sec1_flag1 =1'b0;
sec_cnt2=32'h00000000;
toggle_flag2 =1'b0;
sec1_flag2 =1'b0;
cntw =24'h000000;
next = 10'b0000000000;
tsw = 8'b00000000;
rs_r = 1'b0;
rw_r = 1'b0;
en_r = 1'b0;
//CUR=4'b0000;
//COUNTER_OUT=4'b1111;
// addrs1=8'h11;
// addrs2=8'h22;
// addrs3=8'h33;
// addrs4=8'h44;
//caddrs1=12'b101010101010;
end
//parameter F50M0000_cnt1=32'h000001f4;//10/30動作 10usec
parameter F50M0000_cnt1=32'h00000032;
// parameter F50M0000_cnt1=32'h00000032;
// parameter F50M0000_cnt1=32'h00000004;
parameter F50M0000_cnt2=32'h00000002;
always@(posedge CLK)
begin
if(sec_cnt1 == F50M0000_cnt1) begin
// if(sec_cnt1 == 32'h00000004) begin
sec_cnt1 <= 32'h00000000 ; //counter counting up to the parameter
sec1_flag1 <= 1'b1;
end else begin
sec_cnt1 <= sec_cnt1 + 1 ;
sec1_flag1 <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag1 == 1'b1 )begin
toggle_flag1 <= !toggle_flag1 ;
end
end
assign SHIFT_CLK =!toggle_flag1;
always@(posedge CLK)
begin
if(sec_cnt2 == F50M0000_cnt2) begin
// if(sec_cnt1 == 32'h00000004) begin
sec_cnt2 <= 32'h00000000 ; //counter counting up to the parameter
sec1_flag2 <= 1'b1;
end else begin
sec_cnt2 <= sec_cnt2 + 1 ;
sec1_flag2 <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag2 == 1'b1 )begin
toggle_flag2 <= !toggle_flag2 ;
end
end
always@(negedge RST or posedge toggle_flag2 ) //or posedge EN)11/16
//always@(negedge RST or posedge SHIFT_CLK) //10/31
// always@(negedge RST or posedge CLK ) //or posedge EN)
begin if(RST ==1'b0)begin
//chara_addrs1 <=16'h3031;
//chara_addrs2 <=16'h3032;
//chara_addrs3 <=16'h3033;
//chara_addrs4 <=16'h3034;
//chara_data1 <=16'h3435;
//end else begin
//end else if(EN==1'b1)begin
end else begin
//case(addrs1[3:0])
case(erdata[11:8])
4'b0000 : chara_addrs1[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs1[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs1[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs1[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs1[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs1[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs1[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs1[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs1[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs1[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs1[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs1[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs1[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs1[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs1[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs1[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs1[7:0]<= 8'h31;
endcase
// case(addrs1[7:4])
case(erdata[15:12])
4'b0000 : chara_addrs1[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs1[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs1[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs1[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs1[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs1[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs1[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs1[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs1[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs1[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs1[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs1[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs1[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs1[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs1[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs1[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs1[15:8]<= 8'h32;
endcase
// case(addrs2[3:0])
case(erdata[19:16])
4'b0000 : chara_addrs2[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs2[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs2[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs2[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs2[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs2[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs2[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs2[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs2[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs2[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs2[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs2[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs2[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs2[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs2[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs2[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs2[7:0] <= 8'h33;
endcase
// case(addrs2[7:4])
/* case(erdata[19:16])
4'b0000 : chara_addrs2[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs2[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs2[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs2[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs2[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs2[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs2[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs2[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs2[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs2[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs2[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs2[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs2[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs2[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs2[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs2[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs2[15:8] <= 8'h34;
endcase*/
case(erdata[23:20])
4'b0000 : chara_addrs3[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs3[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs3[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs3[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs3[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs3[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs3[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs3[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs3[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs3[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs3[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs3[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs3[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs3[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs3[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs3[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs3[7:0] <= 8'h35;
endcase
case(erdata[27:24])
4'b0000 : chara_addrs3[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs3[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs3[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs3[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs3[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs3[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs3[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs3[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs3[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs3[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs3[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs3[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs3[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs3[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs3[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs3[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs3[15:8] <= 8'h36;
endcase
case(erdata[31:28])
4'b0000 : chara_addrs4[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs4[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs4[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs4[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs4[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs4[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs4[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs4[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs4[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs4[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs4[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs4[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs4[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs4[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs4[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs4[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs4[7:0] <= 8'h36;
endcase
case(erdata[35:32])
4'b0000 : chara_addrs4[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs4[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs4[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs4[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs4[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs4[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs4[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs4[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs4[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs4[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs4[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs4[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs4[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs4[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs4[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs4[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs4[15:8] <= 8'h37;
endcase
case(erdata[3:0])
4'b0000 : chara_datain[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_datain[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_datain[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_datain[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_datain[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_datain[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_datain[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_datain[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_datain[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_datain[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_datain[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_datain[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_datain[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_datain[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_datain[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_datain[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_datain[7:0] <= 8'h36;
endcase
case(erdata[7:4])
4'b0000 : chara_datain[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_datain[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_datain[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_datain[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_datain[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_datain[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_datain[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_datain[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_datain[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_datain[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_datain[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_datain[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_datain[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_datain[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_datain[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_datain[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_datain[15:8] <= 8'h37;
endcase
case(loadcnt[3:0])
4'b0000 : chara_data1[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_data1[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_data1[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_data1[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_data1[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_data1[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_data1[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_data1[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_data1[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_data1[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_data1[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_data1[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_data1[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_data1[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_data1[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_data1[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_data1[7:0] <= 8'h37;
endcase
case(loadcnt[7:4])
4'b0000 : chara_data1[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_data1[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_data1[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_data1[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_data1[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_data1[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_data1[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_data1[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_data1[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_data1[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_data1[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_data1[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_data1[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_data1[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_data1[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_data1[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_data1[15:8] <= 8'h37;
endcase
case(erdatanxt[11:8])
4'b0000 : chara_addrt1[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrt1[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrt1[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrt1[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrt1[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrt1[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrt1[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrt1[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrt1[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrt1[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrt1[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrt1[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrt1[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrt1[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrt1[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrt1[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrt1[7:0]<= 8'h31;
endcase
// case(addrs1[7:4])
case(erdatanxt[15:12])
4'b0000 : chara_addrt1[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrt1[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrt1[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrt1[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrt1[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrt1[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrt1[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrt1[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrt1[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrt1[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrt1[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrt1[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrt1[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrt1[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrt1[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrt1[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs1[15:8]<= 8'h32;
endcase
// case(addrs2[3:0])
case(erdatanxt[19:16])
4'b0000 : chara_addrt2[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrt2[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrt2[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrt2[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrt2[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrt2[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrt2[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrt2[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrt2[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrt2[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrt2[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrt2[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrt2[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrt2[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrt2[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrt2[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrt2[7:0] <= 8'h33;
endcase
// case(addrs2[7:4])
/* case(erdata[19:16])
4'b0000 : chara_addrs2[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrs2[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrs2[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrs2[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrs2[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrs2[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrs2[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrs2[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrs2[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrs2[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrs2[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrs2[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrs2[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrs2[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrs2[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrs2[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrs2[15:8] <= 8'h34;
endcase*/
case(erdatanxt[23:20])
4'b0000 : chara_addrt3[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrt3[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrt3[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrt3[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrt3[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrt3[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrt3[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrt3[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrt3[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrt3[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrt3[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrt3[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrt3[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrt3[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrt3[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrt3[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrt3[7:0] <= 8'h35;
endcase
case(erdatanxt[27:24])
4'b0000 : chara_addrt3[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrt3[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrt3[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrt3[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrt3[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrt3[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrt3[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrt3[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrt3[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrt3[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrt3[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrt3[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrt3[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrt3[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrt3[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrt3[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrt3[15:8] <= 8'h36;
endcase
case(erdatanxt[31:28])
4'b0000 : chara_addrt4[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrt4[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrt4[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrt4[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrt4[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrt4[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrt4[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrt4[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrt4[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrt4[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrt4[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrt4[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrt4[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrt4[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrt4[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrt4[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrt4[7:0] <= 8'h36;
endcase
case(erdatanxt[35:32])
4'b0000 : chara_addrt4[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_addrt4[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_addrt4[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_addrt4[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_addrt4[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_addrt4[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_addrt4[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_addrt4[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_addrt4[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_addrt4[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_addrt4[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_addrt4[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_addrt4[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_addrt4[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_addrt4[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_addrt4[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_addrt4[15:8] <= 8'h37;
endcase
case(erdatanxt[3:0])
4'b0000 : chara_dataint[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_dataint[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_dataint[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_dataint[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_dataint[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_dataint[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_dataint[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_dataint[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_dataint[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_dataint[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_dataint[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_dataint[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_dataint[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_dataint[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_dataint[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_dataint[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_dataint[7:0] <= 8'h36;
endcase
case(erdatanxt[7:4])
4'b0000 : chara_dataint[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_dataint[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_dataint[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_dataint[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_dataint[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_dataint[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_dataint[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_dataint[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_dataint[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_dataint[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_dataint[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_dataint[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_dataint[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_dataint[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_dataint[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_dataint[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_dataint[15:8] <= 8'h37;
endcase
case(loadcntnxt[3:0])
4'b0000 : chara_data2[7:0]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_data2[7:0]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_data2[7:0]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_data2[7:0]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_data2[7:0]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_data2[7:0]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_data2[7:0]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_data2[7:0]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_data2[7:0]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_data2[7:0]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_data2[7:0]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_data2[7:0]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_data2[7:0]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_data2[7:0]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_data2[7:0]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_data2[7:0]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_data2[7:0] <= 8'h37;
endcase
case(loadcntnxt[7:4])
4'b0000 : chara_data2[15:8]<= 8'h30 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : chara_data2[15:8]<= 8'h31 ; //'1'繧定｡ｨ遉ｺ
4'b0010 : chara_data2[15:8]<= 8'h32 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : chara_data2[15:8]<= 8'h33 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : chara_data2[15:8]<= 8'h34 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : chara_data2[15:8]<= 8'h35 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : chara_data2[15:8]<= 8'h36 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : chara_data2[15:8]<= 8'h37 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : chara_data2[15:8]<= 8'h38 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : chara_data2[15:8]<= 8'h39 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : chara_data2[15:8]<= 8'h41 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : chara_data2[15:8]<= 8'h42 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : chara_data2[15:8]<= 8'h43 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : chara_data2[15:8]<= 8'h44 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : chara_data2[15:8]<= 8'h45 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : chara_data2[15:8]<= 8'h46 ; //'F'繧定｡ｨ遉ｺ
default: chara_data2[15:8] <= 8'h37;
endcase
// default: chara_addrs4 <= 8'b00000110;
//endcase
end
end
always @( posedge SHIFT_CLK ) begin
//always @( posedge SHIFT_CLK or posedge EN) begin //10/31
//always @( negedge RST or posedge CLK ) begin
if ( RST==1 'b0 ) begin
rs_r <= 1'b0;
rw_r <= 1'b0;
en_r <= 1'b0;
// tsw <= 8 'h00;
tsw <= 8 'h20;//11/1
cntw <= 24 'h000000;
next <= 10'd0;
end else if (cntw == 24 'h0cb735)begin
// end else if (cntw == 24 'h000ccc)begin
cntw <= 24 'h000000;
end else begin
cntw <= cntw + 1'b1;
//delya 50msec rs=0
case (next)
10'd0 : if ( cntw == 24 'd50000 ) begin // all_0 & 50ms_wait rs=0 command 50Mhz count 1 = 1usec 50000 = 50msec
rs_r <= 1'b0;
rw_r <= 1'b0;
en_r <= 1'b0;
tsw <= 8'h0;
cntw <= 24'h000000;
next <= 10'd1;
end
//3h 8bitmode 1
10'd1 : if ( cntw == 24 'd1 ) begin //8bit_mode rs=0
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 10'd2;
end
10'd2 : if ( cntw == 24 'd1 ) begin //en_hold_1us rs=0
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd3;
end
//3h 8bitmode 2
10'd3 : if ( cntw == 24 'd5000 ) begin //8bit_mode & 5ms_wait rs=0
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 10'd4;
end
10'd4 : if ( cntw == 24 'd1 ) begin // rs=0
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd5;
end
//3h 8bitmode 3
10'd5 : if ( cntw == 24 'd1000 ) begin //8bit_mode & 1ms_wait rs=0
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 10'd6;
end
10'd6 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd7;
end
//4bit mode 20h half byte only
10'd7 : if ( cntw == 24 'd5000 ) begin //Function set("4"bit_mode & 2disp) & 5ms_wait rs=0
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd8;
end
10'd8 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd900;
end
//2gyouhyouji 28h //8bitmode 38h
10'd900 : if ( cntw == 24 'd5000 ) begin //Function set("4"bit_mode & 2disp) & 5ms_wait
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd901;
end
10'd901 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd902;
end
10'd902 : if ( cntw == 24 'd5000 ) begin //Function set("4"bit_mode & 2disp) & 5ms_wait
en_r <= 1'b1;
tsw <= 8'h80;
cntw <= 24'h00;
next <= 10'd903;
end
10'd903 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd904;
end
//disp on off/ 08h
10'd904 : if ( cntw == 24 'd50 ) begin //disp_on
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd905;
end
10'd905 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd906;
end
10'd906 : if ( cntw == 24 'd50 ) begin //disp_on
en_r <= 1'b1;
tsw <= 8'hc0;//E0
cntw <= 24'h00;
next <= 10'd907;
end
10'd907 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd908;
end
// disp clear 01h
10'd908 : if ( cntw == 24 'd50 ) begin //disp_clear
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd909;
end
10'd909 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd910;
end
10'd910 : if ( cntw == 24 'd50 ) begin //disp_clear
en_r <= 1'b1;
tsw <= 8'h10;//E0
cntw <= 24'h00;
next <= 10'd911;
end
10'd911 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd912;
end
//entrymode 04h
10'd912 : if ( cntw == 24 'd16000 ) begin //entrymode_on
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd913;
end
10'd913 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd914;
end
10'd914 : if ( cntw == 24 'd50 ) begin //entrymode_on
en_r <= 1'b1;
tsw <= 8'h60; //60
cntw <= 24'h00;
next <= 10'd915;
end
10'd915 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd916;
end
//display on 06h
10'd916 : if ( cntw == 24 'd15000 ) begin //address指定
en_r <= 1'b1;
tsw <= 8'h80;
cntw <= 24'h00;
next <= 10'd917;
end
10'd917 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd918;
end
10'd918 : if ( cntw == 24 'd50 ) begin //
en_r <= 1'b1;
tsw <= 8'h00;//F0
cntw <= 24'h00;
next <= 10'd919;
end
10'd919 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd22;
end
//rs ->1 command end
10'd22 : if ( cntw == 24 'd50 ) begin //rs_enb
rs_r <= 1'b1;
cntw <= 24'h00;
next <= 10'd23;
end
//character out 1gyou 1moji MSB->LSB
//1-1
10'd23 : if ( cntw == 24 'd50 ) begin //character_out L 4ch
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[127:124];
tsw[7:4] <= 4'h4;
cntw <= 24'h00;
next <= 10'd24;
end
10'd24 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd25;
end
10'd25 : if ( cntw == 24 'd50 ) begin //character_out L
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[123:120];
tsw[7:4] <= 4'hc;
cntw <= 24'h00;
next <= 10'd26;
end
10'd26 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd27;
end
//1-2
10'd27 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw[7:4] <= chara_data1[119:116];
tsw[7:4]<=chara_data1[15:12];
cntw <= 24'h00;
next <= 10'd28;
end
10'd28 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd29;
end
10'd29 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[115:112];
tsw[7:4]<= chara_data1[11:8];
cntw <= 24'h00;
next <= 10'd30;
end
10'd30 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd31;
end
//1-3
10'd31 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[111:108];
tsw[7:4]<=chara_data1[7:4];
cntw <= 24'h00;
next <= 10'd32;
end
10'd32 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd33;
end
10'd33 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[107:104];
tsw[7:4]<=chara_data1[3:0];
cntw <= 24'h00;
next <= 10'd34;
end
10'd34 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd35;
end
//1-4
10'd35 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[103:100];
tsw[7:4]<=4'h2;
cntw <= 24'h00;
next <= 10'd36;
end
10'd36 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd37;
end
10'd37 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[99:96];
tsw[7:4]<=4'h0;
cntw <= 24'h00;
next <= 10'd38;
end
10'd38 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd39;
end
//1-5
10'd39 : if ( cntw == 24 'd50 ) begin //character_out
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[95:92];
tsw[7:4] <=chara_addrs4[15:12];
cntw <= 24'h00;
next <= 10'd40;
end
10'd40 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd41;
end
10'd41 : if ( cntw == 24 'd50 ) begin //character_out
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[91:88];
tsw[7:4] <=chara_addrs4[11:8];
cntw <= 24'h00;
next <= 10'd42;
end
10'd42 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd43;
end
//1-6
10'd43 : if ( cntw == 24 'd50 ) begin //character_out c
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[87:84];
tsw[7:4]<=chara_addrs4[7:4];
cntw <= 24'h00;
next <= 10'd44;
end
10'd44 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd45;
end
10'd45 : if ( cntw == 24 'd50 ) begin //character_out c
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[83:80];
tsw[7:4]<=chara_addrs4[3:0];
cntw <= 24'h00;
next <= 10'd46;
end
10'd46 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd48;
end
//1-7
10'd48 : if ( cntw == 24 'd50 ) begin //character_out o
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[79:76];
tsw[7:4]<=chara_addrs3[15:12];
cntw <= 24'h00;
next <= 10'd49;
end
10'd49 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd50;
end
10'd50 : if ( cntw == 24 'd50 ) begin //character_out o
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[75:72];
tsw[7:4]<=chara_addrs3[11:8];
cntw <= 24'h00;
next <= 10'd51;
end
10'd51 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 810'd52;
end
//1-8
10'd52 : if ( cntw == 24 'd50 ) begin //character_out u
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[71:68];
tsw[7:4]<=chara_addrs3[7:4];
cntw <= 24'h00;
next <= 10'd53;
end
10'd53 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd54;
end
10'd54 : if ( cntw == 24 'd50 ) begin //character_out u
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[67:64];
tsw[7:4]<=chara_addrs3[3:0];
cntw <= 24'h00;
next <= 10'd55;
end
10'd55 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd56;
end
//1-9
10'd56 : if ( cntw == 24 'd50 ) begin //character_out n
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[63:60];
tsw[7:4]<=chara_addrs2[7:4];
cntw <= 24'h00;
next <= 10'd57;
end
10'd57 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd58;
end
10'd58 : if ( cntw == 24 'd50 ) begin //character_out n
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[59:56];
tsw[7:4]<=chara_addrs2[3:0];
cntw <= 24'h00;
next <= 10'd60;
end
10'd60 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd61;
end
//1-10
10'd61 : if ( cntw == 24 'd50 ) begin //character_out t
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[55:52];
tsw[7:4]<=chara_addrs1[15:12];
cntw <= 24'h00;
next <= 10'd62;
end
10'd62 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd63;
end
10'd63 : if ( cntw == 24 'd50 ) begin //character_out t
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[51:48];
tsw[7:4]<=chara_addrs1[11:8];
cntw <= 24'h00;
next <= 10'd64;
end
10'd64 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd65;
end
//1-11
10'd65 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[47:44];
tsw[7:4]<=chara_addrs1[7:4];
cntw <= 24'h00;
next <= 10'd66;
end
10'd66 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd67;
end
10'd67 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[43:40];
tsw[7:4]<=chara_addrs1[3:0];
cntw <= 24'h00;
next <= 10'd68;
end
10'd68 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd70;
end
//1-12
10'd70 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[39:36];
tsw[7:4]<=4'h2;
cntw <= 24'h00;
next <= 10'd71;
end
10'd71 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd72;
end
10'd72 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[35:32];
tsw[7:4]<=4'h0;
cntw <= 24'h00;
next <= 10'd73;
end
10'd73 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd74;
end
//1-13
10'd74 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[31:28];
tsw[7:4]<=4'h3;
cntw <= 24'h00;
next <= 10'd75;
end
10'd75 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd76;
end
10'd76 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[27:24];
tsw[7:4]<=4'h0;
cntw <= 24'h00;
next <= 10'd77;
end
10'd77 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd78;
end
//1-14
10'd78 : if ( cntw == 24 'd50 ) begin //character_out x 78h
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[23:20];
tsw[7:4]<=4'h7;
cntw <= 24'h00;
next <= 10'd79;
end
10'd79 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd80;
end
10'd80 : if ( cntw == 24 'd50 ) begin //character_out x 78h
en_r <= 1'b1;
// tsw[7:4] <= mode_lcd_disp[19:16];
tsw[7:4]<=4'h8;
cntw <= 24'h00;
next <= 10'd81;
end
10'd81 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd82;
end
//1-15
10'd82 : if ( cntw == 24 'd50 ) begin //character_out datain[15:8]
en_r <= 1'b1;
// tsw <= mode_lcd_disp[15:8];
tsw[7:4]<=chara_datain[15:12];
cntw <= 24'h00;
next <= 10'd83;
end
10'd83 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd84;
end
10'd84 : if ( cntw == 24 'd50 ) begin //character_out
en_r <= 1'b1;
// tsw <= mode_lcd_disp[15:8];
tsw[7:4]<=chara_datain[11:8];
cntw <= 24'h00;
next <= 10'd85;
end
10'd85 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd86;
end
//1-16
10'd86 : if ( cntw == 24 'd50 ) begin //character_out datain[7:0]
en_r <= 1'b1;
// tsw <= mode_lcd_disp[7:0];
tsw[7:4]<=chara_datain[7:4];
cntw <= 24'h00;
next <= 10'd87;
end
10'd87 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// rs_r <= 1'b0;
next <= 10'd88;
end
10'd88 : if ( cntw == 24 'd50 ) begin //character_out 1
en_r <= 1'b1;
// tsw <= mode_lcd_disp[7:0];
tsw[7:4]<=chara_datain[3:0];
cntw <= 24'h00;
next <= 10'd89;
end
10'd89 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
next <= 10'd90;//90
end
//2nd column start rs_r=0 command
10'd90 : if ( cntw == 24 'd1500 ) begin ////////////////////character_out 2column selected 0x40 1rst 11/6 500->1500
en_r <= 1'b1;
tsw <= 8'hc0;
cntw <= 24'h00;
next <= 10'd91;
end
10'd91 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// rs_r <= 1'b0; //1
next <= 10'd92;
end
10'd92 : if ( cntw == 24 'd500 ) begin ////////////////////character_out 2column selected 0x40 1rst
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd93;
end
10'd93 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b1;
next <= 10'd94;
end
//2-1
10'd94 : if ( cntw == 24 'd50 ) begin //character_out -> 0x7e
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h70;
cntw <= 24'h00;
next <= 10'd95;
end
10'd95 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd96;
end
10'd96 : if ( cntw == 24 'd50 ) begin //character_out ->
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'he0;
cntw <= 24'h00;
next <= 10'd97;
end
10'd97 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd98;
end
//2-2
10'd98 : if ( cntw == 24 'd50 ) begin //character_out d c_cyc_cnt+1
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h60;
tsw[7:4]<=chara_data2[15:12];
cntw <= 24'h00;
next <= 10'd99;
end
10'd99 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd100;
end
10'd100 : if ( cntw == 24 'd50 ) begin //character_out
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h40;
tsw[7:4]<=chara_data2[11:8];
cntw <= 24'h00;
next <= 10'd101;
end
10'd101 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd102;
end
//2-3 72h r
10'd102 : if ( cntw == 24 'd50 ) begin //character_out
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h70;
tsw[7:4]<=chara_data2[7:4];
cntw <= 24'h00;
next <= 10'd103;
end
10'd103 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd104;
end
10'd104 : if ( cntw == 24 'd50 ) begin //character_out
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h20;
tsw[7:4]<=chara_data2[3:0];
cntw <= 24'h00;
next <= 10'd105;
end
10'd105 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd106;
end
//2-4
10'd106 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd107;
end
10'd107 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd108;
end
10'd108 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd109;
end
10'd109 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd110;
end
//2-5
10'd110 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt4[15:12];
cntw <= 24'h00;
next <= 10'd111;
end
10'd111 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd112;
end
10'd112 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt4[11:8];
cntw <= 24'h00;
next <= 10'd113;
end
10'd113 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd114;
end
//2-6
10'd114 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt4[7:4];
cntw <= 24'h00;
next <=10'd115;
end
10'd115 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd116;
end
10'd116 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt4[3:0];
cntw <= 24'h00;
next <=10'd117;
end
10'd117 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd118;
end
//2-7
10'd118 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt3[15:12];
cntw <= 24'h00;
next <=10'd119;
end
10'd119 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd120;
end
10'd120 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt3[11:8];
cntw <= 24'h00;
next <=10'd121;
end
10'd121 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd122;
end
//2-8
10'd122 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt3[7:4];
cntw <= 24'h00;
next <= 10'd123;
end
10'd123 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd124;
end
10'd124 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt3[3:0];
cntw <= 24'h00;
next <= 10'd125;
end
10'd125 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd126;
end
//2-9
10'd126 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt2[7:4];
cntw <= 24'h00;
next <= 10'd127;
end
10'd127 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd128;
end
10'd128 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt2[3:0];
cntw <= 24'h00;
next <= 10'd129;
end
10'd129 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd130;
end
//2-10
10'd130 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw[7:4] <= chara_addrt1[15:12];
cntw <= 24'h00;
next <= 10'd138;
end
10'd138 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd139;
end
10'd139 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw[7:4] <= chara_addrt1[11:8];
cntw <= 24'h00;
next <= 10'd140;
end
10'd140 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd141;
end
//2-11
10'd141 : if ( cntw == 24 'd50) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw[7:4] <= chara_addrt1[7:4];
cntw <= 24'h00;
next <= 10'd142;
end
10'd142 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd143;
end
10'd143 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw[7:4] <= chara_addrt1[3:0];
cntw <= 24'h00;
next <= 10'd144;
end
10'd144 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd145;
end
//2-12
10'd145 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd146;
end
10'd146 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd147;
end
10'd147 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd148;
end
10'd148 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd149;
end
//2-13
10'd149 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h30;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 10'd150;
end
10'd150 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd151;
end
10'd151 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h00;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 10'd152;
end
10'd152 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd153;
end
//2-14
10'd153 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h70;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 10'd154;
end
10'd154 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd155;
end
10'd155 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h80;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 10'd156;
end
10'd156 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd157;
end
//2-15
10'd157 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw[7:4] <= chara_dataint[15:12];
cntw <= 24'h00;
next <= 10'd159;
end
10'd159 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd160;
end
10'd160 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw[7:4] <= chara_dataint[11:8];
cntw <= 24'h00;
next <= 10'd161;
end
10'd161 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd162;
end
//2-16
10'd162 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw[7:4] <= chara_dataint[7:4];
cntw <= 24'h00;
next <= 10'd163;
end
10'd163 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd164;
// next <= 8'd94;
end
10'd164 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw[7:4] <= chara_dataint[3:0];
cntw <= 24'h00;
next <= 10'd165;
end
10'd165 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// next <= 10'd166;
next <= 10'd166;
end
/* 8'd82 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'h83; //8'hxx
end
*/
//2 end
10'd166 : if ( cntw == 24 'd50 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
// next <= 8'd84;
next <= 10'd167; //10/28
end
10'd167 : if ( cntw == 24 'd1500 ) begin //character_out 2column selected 0x40 update
en_r <= 1'b1;
tsw <= 8'hc0;
// tsw <= 8'hcc;
cntw <= 24'h00;
next <= 10'd168;
end
10'd168 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// rs_r <= 1'b1;
next <= 10'd169;
end
10'd169 : if ( cntw == 24 'd500 ) begin //character_out 2column selected 0x40 update
en_r <= 1'b1;
tsw <= 8'h00;
// tsw <= 8'hcc;
cntw <= 24'h00;
next <= 10'd170;
end
10'd170 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b1;
next <= 10'd171;
end
//2 2-1
10'd171 : if ( cntw == 24 'd50 ) begin //character_out l ach
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h70;
cntw <= 24'h00;
next <= 10'd172;
end
10'd172 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd173;
end
10'd173 : if ( cntw == 24 'd50 ) begin //character_out A
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'he0;
cntw <= 24'h00;
next <= 10'd174;
end
10'd174 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd175;
end
//2 2-2
10'd175 : if ( cntw == 24 'd50 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h60;
tsw[7:4]<=chara_data2[15:12];
cntw <= 24'h00;
next <= 10'd176;
end
10'd176 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd177;
end
10'd177 : if ( cntw == 24 'd50 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h40;
tsw[7:4]<=chara_data2[11:8];
cntw <= 24'h00;
next <= 10'd178;
end
10'd178 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd179;
end
//2 2-3
10'd179 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h70;
tsw[7:4]<=chara_data2[7:4];
cntw <= 24'h00;
next <= 10'd180;
end
10'd180 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd181;
end
10'd181 : if ( cntw == 24 'd50 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h20;
tsw[7:4]<=chara_data2[3:0];
cntw <= 24'h00;
next <= 10'd182;
end
10'd182 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd183;
end
//2 2-4
10'd183 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd185;
end
10'd185 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd186;
end
10'd186 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd187;
end
10'd187 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd188;
end
// 2-5
10'd188 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt4[15:12];
cntw <= 24'h00;
next <= 10'd189;
end
10'd189 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd190;
end
10'd190 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt4[11:8];
cntw <= 24'h00;
next <= 10'd191;
end
10'd191 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd192;
end
//2 2-6
10'd192 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt4[7:4];
cntw <= 24'h00;
next <= 10'd193;
end
10'd193 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd194;
end
10'd194 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt4[3:0];
cntw <= 24'h00;
next <= 10'd195;
end
10'd195 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd196;
end
//2 2-7
10'd196 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt3[15:12];
cntw <= 24'h00;
next <= 10'd197;
end
10'd197 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd198;
end
10'd198 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt3[11:8];
cntw <= 24'h00;
next <= 10'd199;
end
10'd199 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd201;
end
//2 2-8
10'd201 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt3[7:4];
cntw <= 24'h00;
next <= 10'd202;
end
10'd202 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd203;
end
10'd203 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt3[3:0];
cntw <= 24'h00;
next <= 10'd204;
end
10'd204 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd205;
end
//2 2-9
10'd205 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt2[7:4];
cntw <= 24'h00;
next <= 10'd206;
end
10'd206 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd207;
end
10'd207 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw[7:4] <= chara_addrt2[3:0];
cntw <= 24'h00;
next <= 10'd208;
end
10'd208 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd209;
end
//2 /2-10
10'd209 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw[7:4] <= chara_addrt1[15:12];
cntw <= 24'h00;
next <= 10'd210;
end
10'd210 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd211;
end
10'd211 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw[7:4] <= chara_addrt1[11:8];
cntw <= 24'h00;
next <= 10'd212;
end
10'd212 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd213;
end
//2 2-11
10'd213 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw[7:4] <= chara_addrt1[7:4];
cntw <= 24'h00;
next <= 10'd214;
end
10'd214 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd215;
end
10'd215 : if ( cntw == 24 'd50 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw[7:4] <= chara_addrt1[3:0];
cntw <= 24'h00;
next <= 10'd216;
end
10'd216 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd217;
end
//2 2-12
10'd217 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 10'd218;
end
10'd218 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd219;
end
10'd219 : if ( cntw == 24 'd50 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd220;
end
10'd220 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd221;
end
//2 2-13
10'd221 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h30;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 10'd222;
end
10'd222 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd223;
end
10'd223 : if ( cntw == 24 'd50 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h00;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 10'd224;
end
10'd224 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd225;
end
//2 2-14 78h
10'd225 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h70;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 10'd226;
end
10'd226 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd227;
end
10'd227 : if ( cntw == 24 'd50 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h80;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 10'd228;
end
10'd228 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd229;
end
//2 2-15
10'd229 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw[7:4] <= chara_dataint[15:12];
cntw <= 24'h00;
next <= 10'd230;
end
10'd230 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd231;
end
10'd231 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw[7:4] <= chara_dataint[11:8];
cntw <= 24'h00;
next <= 10'd232;
end
10'd232 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 10'd233;
end
//2 2-16
10'd233 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw[7:4] <= chara_dataint[7:4];
cntw <= 24'h00;
next <= 10'd234;
end
10'd234 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
// rs_r<=1'b0;//10/31
next <= 10'd235;
// next <= 8'd94;
end
10'd235 : if ( cntw == 24 'd50 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw[7:4] <= chara_dataint[3:0];
cntw <= 24'h00;
next <= 10'd236;
end
10'd236 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r<=1'b0;//10/31
next <= 10'd237;
// next <= 8'd94;
end
/* 8'd82 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'h83; //8'hxx
end
*/
/*8'd118 : if ( cntw == 24 'd500 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
// next <= 8'd84;
next <= 8'd119; //10/28
end */
10'd237 : if ( cntw == 24 'd1500 ) begin //character_out 1column selected 0x00
en_r <= 1'b1;
// tsw <= 8'hc0;
tsw <= 8'h80;
cntw <= 24'h00;
next <= 10'd238;
end
10'd238 : if ( cntw == 24 'd1 ) begin
rw_r <= 1'b0;
// rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd239;
end
10'd239 : if ( cntw == 24 'd50 ) begin //character_out 1column selected 0x00
en_r <= 1'b1;
// tsw <= 8'hc0;
tsw <= 8'h00;
cntw <= 24'h00;
next <= 10'd240;
end
10'd240 : if ( cntw == 24 'd1 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <=10'd241;
end
10'd241:if(cntw==24'd1 )begin//&& CUR !=4'b1000)begin
next <= 10'd912;//83 22
//end else begin
// next <=8'd15;
end
endcase
end
end
/*
always @( posedge SHIFT_CLK ) begin
//always @( posedge SHIFT_CLK or posedge EN) begin //10/31
if ( RST==1 'b0 ) begin
rs_r <= 1'b0;
rw_r <= 1'b0;
en_r <= 1'b0;
// tsw <= 8 'h00;
tsw <= 8 'h20;//11/1
cntw <= 24 'h000000;
next <= 8'd0;
end else if (cntw == 24 'h0cb735)begin
// end else if (cntw == 24 'h000ccc)begin
cntw <= 24 'h000000;
end else begin
cntw <= cntw + 1'b1;
case (next)
8'd0 : if ( cntw == 24 'd50000 ) begin // all_0 & 50ms_wait
rs_r <= 1'b0;
rw_r <= 1'b0;
en_r <= 1'b0;
tsw <= 8'h0;
cntw <= 24'h000000;
next <= 8'd1;
end
8'd1 : if ( cntw == 24 'd1 ) begin //8bit_mode
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 8'd2;
end
8'd2 : if ( cntw == 24 'd1 ) begin //en_hold_1us
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd3;
end
8'd3 : if ( cntw == 24 'd5000 ) begin //8bit_mode & 5ms_wait
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 8'd4;
end
8'd4 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd5;
end
8'd5 : if ( cntw == 24 'd1000 ) begin //8bit_mode & 1ms_wait
en_r <= 1'b1;
tsw <= 8'h30;
cntw <= 24'h00;
next <= 8'd6;
end
8'd6 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd7;
end
8'd7 : if ( cntw == 24 'd5000 ) begin //Function set(8bit_mode & 2disp) & 5ms_wait
en_r <= 1'b1;
tsw <= 8'h38;
cntw <= 24'h00;
next <= 8'd8;
end
8'd8 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd9;
end
8'd9 : if ( cntw == 24 'd1000 ) begin //disp_clear
en_r <= 1'b1;
tsw <= 8'h01;
cntw <= 24'h00;
next <= 8'd10;
end
8'd10 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd11;
end
8'd11 : if ( cntw == 24 'd2000 ) begin //entrymode_on
en_r <= 1'b1;
tsw <= 8'h06;
cntw <= 24'h00;
next <= 8'd12;
end
8'd12 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd13;
end
8'd13 : if ( cntw == 24 'd1000 ) begin //disp_on & cursor_on & blink_on
en_r <= 1'b1;
tsw <= 8'h0F;
cntw <= 24'h00;
next <= 8'd14;
end
8'd14 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd15;
end
8'd15 : if ( cntw == 24 'd500 ) begin //rs_enb
rs_r <= 1'b1;
cntw <= 24'h00;
next <= 8'd16;
end
8'd16 : if ( cntw == 24 'd1 ) begin //character_out w
en_r <= 1'b1;
tsw <= mode_lcd_disp[127:120];
cntw <= 24'h00;
next <= 8'd17;
end
8'd17 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd18;
end
8'd18 : if ( cntw == 24 'd500 ) begin //character_out r
en_r <= 1'b1;
tsw <= mode_lcd_disp[119:112];
cntw <= 24'h00;
next <= 8'd19;
end
8'd19 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd20;
end
8'd20 : if ( cntw == 24 'd500 ) begin //character_out r
en_r <= 1'b1;
tsw <= mode_lcd_disp[111:104];
cntw <= 24'h00;
next <= 8'd21;
end
8'd21 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd22;
end
8'd22 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
tsw <= mode_lcd_disp[103:96];
cntw <= 24'h00;
next <= 8'd23;
end
8'd23 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd24;
end
8'd24 : if ( cntw == 24 'd500 ) begin //character_out
en_r <= 1'b1;
tsw <= mode_lcd_disp[95:88];
cntw <= 24'h00;
next <= 8'd25;
end
8'd25 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd26;
end
8'd26 : if ( cntw == 24 'd500 ) begin //character_out c
en_r <= 1'b1;
tsw <= mode_lcd_disp[87:80];
cntw <= 24'h00;
next <= 8'd27;
end
8'd27 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd28;
end
8'd28 : if ( cntw == 24 'd500 ) begin //character_out o
en_r <= 1'b1;
tsw <= mode_lcd_disp[79:72];
cntw <= 24'h00;
next <= 8'd29;
end
8'd29 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd30;
end
8'd30 : if ( cntw == 24 'd500 ) begin //character_out u
en_r <= 1'b1;
tsw <= mode_lcd_disp[71:64];
cntw <= 24'h00;
next <= 8'd31;
end
8'd31 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd32;
end
8'd32 : if ( cntw == 24 'd500 ) begin //character_out n
en_r <= 1'b1;
tsw <= mode_lcd_disp[63:56];
cntw <= 24'h00;
next <= 8'd33;
end
8'd33 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd34;
end
8'd34 : if ( cntw == 24 'd500 ) begin //character_out t
en_r <= 1'b1;
tsw <= mode_lcd_disp[55:48];
cntw <= 24'h00;
next <= 8'd35;
end
8'd35 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd36;
end
8'd36 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
tsw <= mode_lcd_disp[47:40];
cntw <= 24'h00;
next <= 8'd37;
end
8'd37 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd38;
end
8'd38 : if ( cntw == 24 'd500 ) begin //character_out x
en_r <= 1'b1;
tsw <= mode_lcd_disp[39:32];
cntw <= 24'h00;
next <= 8'd39;
end
8'd39 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd40;
end
8'd40 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
tsw <= mode_lcd_disp[31:24];
cntw <= 24'h00;
next <= 8'd41;
end
8'd41 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd42;
end
8'd42 : if ( cntw == 24 'd500 ) begin //character_out 6
en_r <= 1'b1;
tsw <= mode_lcd_disp[23:16];
cntw <= 24'h00;
next <= 8'd43;
end
8'd43 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd44;
end
8'd44 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
// tsw <= mode_lcd_disp[15:8];
tsw<=chara_datain[15:8];
cntw <= 24'h00;
next <= 8'd45;
end
8'd45 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd46;
end
8'd46 : if ( cntw == 24 'd500 ) begin //character_out 1
en_r <= 1'b1;
// tsw <= mode_lcd_disp[7:0];
tsw<=chara_datain[7:0];
cntw <= 24'h00;
next <= 8'd47;
end
8'd47 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
next <= 8'd48;
end
//2nd column start
8'd48 : if ( cntw == 24 'd500 ) begin ////////////////////character_out 2column selected 0x40 1rst
en_r <= 1'b1;
tsw <= 8'hc0;
cntw <= 24'h00;
next <= 8'd49;
end
8'd49 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b1;
next <= 8'd50;
end
8'd50 : if ( cntw == 24 'd500 ) begin //character_out A
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h41;
cntw <= 24'h00;
next <= 8'd51;
end
8'd51 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd52;
end
8'd52 : if ( cntw == 24 'd500 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h64;
cntw <= 24'h00;
next <= 8'd53;
end
8'd53 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd54;
end
8'd54 : if ( cntw == 24 'd500 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h72;
cntw <= 24'h00;
next <= 8'd55;
end
8'd55 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd56;
end
8'd56 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 8'd57;
end
8'd57 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd58;
end
8'd58 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs4[15:8];
cntw <= 24'h00;
next <= 8'd59;
end
8'd59 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd60;
end
8'd60 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs4[7:0];
cntw <= 24'h00;
next <= 8'd61;
end
8'd61 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd62;
end
8'd62 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs3[15:8];
cntw <= 24'h00;
next <= 8'd63;
end
8'd63 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd64;
end
8'd64 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs3[7:0];
cntw <= 24'h00;
next <= 8'd65;
end
8'd65 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd66;
end
8'd66 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs2[7:0];
cntw <= 24'h00;
next <= 8'd67;
end
8'd67 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd68;
end
8'd68 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw <= chara_addrs1[15:8];
cntw <= 24'h00;
next <= 8'd69;
end
8'd69 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd70;
end
8'd70 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw <= chara_addrs1[7:0];
cntw <= 24'h00;
next <= 8'd71;
end
8'd71 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd72;
end
8'd72 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 8'd73;
end
8'd73 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd74;
end
8'd74 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h30;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 8'd75;
end
8'd75 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd76;
end
8'd76 : if ( cntw == 24 'd500 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h78;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 8'd77;
end
8'd77 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd78;
end
8'd78 : if ( cntw == 24 'd500 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw <= chara_data1[15:8];
cntw <= 24'h00;
next <= 8'd79;
end
8'd79 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd80;
end
8'd80 : if ( cntw == 24 'd500 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw <= chara_data1[7:0];
cntw <= 24'h00;
next <= 8'd81;
end
8'd81 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd83;
// next <= 8'd94;
end
/* 8'd82 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'h83; //8'hxx
end
8'd83 : if ( cntw == 24 'd500 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
// next <= 8'd84;
next <= 8'd84; //10/28
end
8'd84 : if ( cntw == 24 'd500 ) begin //character_out 2column selected 0x40 update
en_r <= 1'b1;
tsw <= 8'hc0;
// tsw <= 8'hcc;
cntw <= 24'h00;
next <= 8'd85;
end
8'd85 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b1;
next <= 8'd86;
end
8'd86 : if ( cntw == 24 'd500 ) begin //character_out A
en_r <= 1'b1;
// tsw <= 8'h20;
// tsw <= 8'h31;
tsw <= 8'h41;
cntw <= 24'h00;
next <= 8'd87;
end
8'd87 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd88;
end
8'd88 : if ( cntw == 24 'd500 ) begin //character_out d
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h64;
cntw <= 24'h00;
next <= 8'd89;
end
8'd89 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd90;
end
8'd90 : if ( cntw == 24 'd500 ) begin //character_out r
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h72;
cntw <= 24'h00;
next <= 8'd91;
end
8'd91 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd92;
end
8'd92 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 8'd93;
end
8'd93 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd94;
end
8'd94 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs4[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs4[15:8];
cntw <= 24'h00;
next <= 8'd95;
end
8'd95 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd96;
end
8'd96 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs4[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs4[7:0];
cntw <= 24'h00;
next <= 8'd97;
end
8'd97 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd98;
end
8'd98 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs3[15:8]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs3[15:8];
cntw <= 24'h00;
next <= 8'd99;
end
8'd99 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd100;
end
8'd100 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs3[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs3[7:0];
cntw <= 24'h00;
next <= 8'd101;
end
8'd101 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd102;
end
8'd102 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs2[7:0]
en_r <= 1'b1;
// tsw <= 8'h20;
tsw <= chara_addrs2[7:0];
cntw <= 24'h00;
next <= 8'd103;
end
8'd103 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd104;
end
8'd104 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs1[15:8]
en_r <= 1'b1;
// tsw <= 8'h32;
tsw <= chara_addrs1[15:8];
cntw <= 24'h00;
next <= 8'd105;
end
8'd105 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd106;
end
8'd106 : if ( cntw == 24 'd500 ) begin //character_out chara_addrs1[7:0]
en_r <= 1'b1;
// tsw <= 8'h31;
tsw <= chara_addrs1[7:0];
cntw <= 24'h00;
next <= 8'd107;
end
8'd107 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd108;
end
8'd108 : if ( cntw == 24 'd500 ) begin //character_out space
en_r <= 1'b1;
tsw <= 8'h20;
cntw <= 24'h00;
next <= 8'd109;
end
8'd109 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd110;
end
8'd110 : if ( cntw == 24 'd500 ) begin //character_out 0
en_r <= 1'b1;
tsw <= 8'h30;
// tsw <= character_hex4;
cntw <= 24'h00;
next <= 8'd111;
end
8'd111 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd112;
end
8'd112 : if ( cntw == 24 'd500 ) begin //character_out x
en_r <= 1'b1;
tsw <= 8'h78;
// tsw <= character_hex3;
cntw <= 24'h00;
next <= 8'd113;
end
8'd113 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd114;
end
8'd114 : if ( cntw == 24 'd500 ) begin //character_out chara_data1[15:8]
en_r <= 1'b1;
// tsw <= 8'h45;
tsw <= chara_data1[15:8];
cntw <= 24'h00;
next <= 8'd115;
end
8'd115 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'd116;
end
8'd116 : if ( cntw == 24 'd500 ) begin //character_out chara_data1[7:0]
en_r <= 1'b1;
// tsw <= 8'h46;
tsw <= chara_data1[7:0];
cntw <= 24'h00;
next <= 8'd117;
end
8'd117 : if ( cntw == 24 'd1 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r<=1'b0;//10/31
next <= 8'd118;
// next <= 8'd94;
end
/* 8'd82 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <= 8'h83; //8'hxx
end
*/
/*8'd118 : if ( cntw == 24 'd500 ) begin
en_r <= 1'b0;
cntw <= 24'h00;
rs_r <= 1'b0;
// next <= 8'd84;
next <= 8'd119; //10/28
end
8'd118 : if ( cntw == 24 'd500 ) begin //character_out 1column selected 0x00
en_r <= 1'b1;
// tsw <= 8'hc0;
tsw <= 8'h80;
cntw <= 24'h00;
next <= 8'd119;
end
8'd119 : if ( cntw == 24 'd500 ) begin
rw_r <= 1'b0;
rs_r <= 1'b0;
en_r <= 1'b0;
cntw <= 24'h00;
next <=8'd120;
end
8'd120:if(cntw==24'd1 )begin//&& CUR !=4'b1000)begin
next <= 10'd15;//83 //15
//end else begin
// next <=8'd15;
end
endcase
end
end
*/
assign db = tsw;
assign rw = rw_r;
assign en = en_r;
assign rs = rs_r;
endmodule
"3.テストベンチソースコード(test bench source code)" †
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Abbreviation
"4.タイミングコンストレインソースコード(constrain file)" †
省略
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5.結果(result) †
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#ref(): File not found: "result1.png" at page "verilog/nand_controller"
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