verilog / SPI_read1

verilog

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1.SPI_read1
1-1.タイミングチャート
1-2.ピン一覧
1-3.ソースコード
1-4.テストベンチソースコード

1.SPI_read1 †

1-1.タイミングチャート †

下記のような構成を考える。

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1-2.ピン一覧 †

1-3.ソースコード †

/* 2018/11/19 Revison beta made LPC<--->SPI conversion pin assignmennts are below. it does'nt meant to be compatible. CLK<--->SCLK FRAME<--->CS LAD3<--->MOSI LAD2<--->MISO

/ †

module SPI_read2 //10/28changed from wa8 (

//port80h reader decoder
CLK, //standard clock
RST,//RST Input
SDATA,//sdata Input,
CS_N,//Manual Input or cs_n
COMOUT,
 SHIFT_CLK,//SCK2
 SEC_CLK,
WRCYC,
SEVEN_SEG_DATA,
SEL,
DSEL,
DSEVEN_SEG_DATA,
WCYC_COUNTER,

//制御信号
 LED_OUT

 	);
	
// input definition LPCBUS//
	input CLK;
	input RST;
	input SDATA;
 	input CS_N;

		 
//output definition//
	output  SHIFT_CLK;
	output SEC_CLK;
	output COMOUT;
	output WRCYC; 
	output [4:1] SEL;
	output reg[7:0] SEVEN_SEG_DATA;
  output [2:1] DSEL;
	output reg[7:0] DSEVEN_SEG_DATA;
	output[7:0] WCYC_COUNTER;
  output[7:0] LED_OUT;
	//	 output[7:0] RDAT;
// register//
	reg [31:0] sec_cnt2 ;
  reg  sec1_flag2 ;
  reg  toggle_flag2 ; 
	reg [31:0] sec_cnt3 ;
  reg  sec1_flag3 ;
  reg  toggle_flag3 ; 
	reg[11:0] rcounter_reg;
	reg sdata;
	reg cs_n;
	wire COMOUT;
	reg wrcyc;
	reg[7:0] seven_seg1_hold;
	reg[7:0] seven_seg2_hold;
	reg[7:0] seven_seg3_hold;
	reg[7:0] seven_seg4_hold;
	reg[7:0] seven_seg_data;
	reg[4:1]sel;
	reg[1:0]enable_seg;
	reg[2:1]dsel;
	reg denable_seg;
	reg[7:0] dseven_seg1_hold;
	reg[7:0] dseven_seg2_hold;
	reg[4:0] cs_counter;
 	
	reg ad0;
	reg ad1;
  reg ad2;
	reg ad3;
	reg ad4;
	reg ad5;
	reg ad6;
	reg ad7;
	reg[7:0] ad;
	reg en80;
	reg[7:0] ld;
	reg[3:0] ld1;
	reg[3:0] ld2;
	reg startflag;
	     //***通信クロック***//
        // reg[31:0] CLK_COUNT;
         //wire SHIFT_CLK;
      
 

  //***parameter definition***//
parameter F33M0000_cnt2=32'h0000d6d8 ;   //High time 0.001666667sec 300bps
//parameter F33M0000_cnt2=32'h00001ADB ; //High time 0.002083335sec 2400bps
//parameter F33M0000_cnt2=32'h000006b6 ;   //High time 0.00005208sec 9600bps
//  parameter F33M0000_cnt2=32'h0000008F ;   //High time 0.00000434sec 115200bps
parameter F33M0000_cnt3=32'h00fbc51f ;//High Time 1sec

 parameter	selinit_value = 4'b0001	;
 parameter dselinit_value =2'b01;
 parameter rcounter_reg_init_value = 12'b100000000000;
 initial	cs_counter = 5'b00000;
 //initial   cs_n <= 1'b1 ;

 
 
 //***7seg Dynamic lighting SHIFT_CLK generation(using serial bouad rate generation too)***//
always@(posedge CLK)
begin
  if(sec_cnt2 == F33M0000_cnt2) begin
	  sec_cnt2 <= 32'h00000000 ; //counter counting up to the parameter
	  sec1_flag2 <= 1'b1; 
	end else begin
	  sec_cnt2 <= sec_cnt2 + 1 ;
	  sec1_flag2 <= 1'b0 ;
	end
end

always@(posedge CLK)
begin
  if(sec1_flag2 == 1'b1 )begin
	 toggle_flag2 <= !toggle_flag2 ;
	end
end

assign SHIFT_CLK =!toggle_flag2;

  //***Serial transmitting interrupt clk SEC_CLK generation***//
always@(posedge CLK)
begin
 //if(SEND_ACTIVE ==1'b0)begin
  if(sec_cnt3 ==F33M0000_cnt3)begin
    sec_cnt3 <= 32'h00000000 ; //counter counting up to the parameter
	  sec1_flag3 <= 1'b1; 
	end else begin
	  sec_cnt3 <= sec_cnt3 + 1 ;
	  sec1_flag3 <= 1'b0 ;
	end
end

always@(posedge CLK)

begin
  if(sec1_flag3 == 1'b1 )begin
	 toggle_flag3 <= !toggle_flag3 ;
	end
end

assign SEC_CLK =!toggle_flag3;

//***Ring counter generation***//

always@(posedge CLK or negedge RST  )
begin
  if(RST == 1'b0 ) begin
	   rcounter_reg <= 12'b000000000001 ;
	end else if(CS_N ==1'b1)begin
	   rcounter_reg <= 12'b000000000001 ;
	end else if( CS_N ==1'b0 )begin
		rcounter_reg <= {rcounter_reg,rcounter_reg[11]};
	end
end

always@(posedge CLK or  negedge RST or negedge CS_N)
 begin
  if(RST == 1'b0 )begin
	   cs_counter<= 5'b00000;
	end else if(CS_N == 1'b0)begin	
		cs_counter <=5'b00000;
  end else if(cs_counter > 5'b10001)begin
  cs_counter <=5'b00000;
	end else begin
   cs_counter <= cs_counter +1'b1;
	end
end

always@*
 begin
 if(RST == 1'b0)begin
   cs_n<= 1'b1;
 end else if(CS_N ==1'b0)begin
  cs_n <= 1'b1;
 end else if(cs_counter >5'b01011)begin
  cs_n <=1'b1;
 end else begin
  cs_n <=1'b0;
 end
 end
   
always@(negedge RST or posedge CLK)
begin
if(RST == 1'b0)begin
  startflag <=1'b0;
end else if(CS_N == 1'b0) 
begin
	 startflag <= 1'b1;
end else begin
   startflag <= 1'b0;
	end
end
  

	//***write cycle starting detection***//

always@(posedge CLK)

begin if(RST ==1'b0)begin
 wrcyc <=1'b0;
    end else if(ad ==8'h06 )begin
   wrcyc <= 1'b1 ; 
	end else if(ad !==8'h06)begin
	 wrcyc <= 1'b0;
	end
	end

assign WRCYC = wrcyc ;

 
always@(posedge SHIFT_CLK or  negedge RST)begin
  if(RST == 1'b0 )begin
	  sel <= selinit_value;
	  end else begin
   sel[4] <= sel[1]	;	//シフト動作を開始する
 sel[3] <= sel[4]	;	//シフト動作を開始する
 sel[2] <= sel[3]	;	//シフト動作を開始する
 sel[1] <= sel[2]	;
   end
end

assign SEL[4:1] = ~sel[4:1];

always@(negedge RST or posedge CLK or posedge rcounter_reg[0]  )
begin if(RST ==1'b0)begin
 seven_seg1_hold <=8'b00000110;
 end else begin
	 if( rcounter_reg[0]==1'b1)
	  	case(ad1)
	1'b0 : seven_seg1_hold<= 8'b00111111 ; //'0'    dot   g   f    e    d    c    b    a
	1'b1 : seven_seg1_hold <= 8'b00000110 ; //'1'
	default: seven_seg1_hold <= 8'b01110001;
	endcase
	end
	end
	
always@(negedge RST or posedge CLK or posedge rcounter_reg[1] )
begin if(RST ==1'b0)begin
  seven_seg2_hold <=8'b01011011;
    end else begin
	  if(rcounter_reg[1]==1'b1)
		  	case(ad2)
	1'b0 : seven_seg2_hold<= 8'b00111111 ; //'0
	1'b1 : seven_seg2_hold <= 8'b00000110 ; //'1'
	 default: seven_seg2_hold <= 8'b01110001;
	endcase
	end
	end
	
always@(negedge RST or posedge CLK or posedge rcounter_reg[2]  )
 begin if(RST ==1'b0)begin
  seven_seg3_hold <=8'b01001111;
  end else begin 
	 if(rcounter_reg[2]==1'b1)
	case(ad3)
	1'b0 : seven_seg3_hold<= 8'b00111111 ; //'0'
	1'b1 : seven_seg3_hold <= 8'b00000110 ; //'1'
  default: seven_seg3_hold <= 8'b01110001;
	endcase
	end
	end

always@(negedge RST or posedge CLK or posedge rcounter_reg[3] )	//4
begin if(RST ==1'b0)begin
 seven_seg4_hold <=8'b01100110;
  end else begin   
	 if(rcounter_reg[3]==1'b1)
	 	case(ad4)
	1'b0 : seven_seg4_hold<= 8'b00111111 ; //'0'
	1'b1 : seven_seg4_hold <= 8'b00000110 ; //'1'
	  default: seven_seg4_hold <= 8'b01110001;
	endcase
end
end

 always@(negedge RST or posedge CLK )//or posedge rcounter_reg[0])
begin if(RST ==1'b0)begin
  ad0 <=1'b0;
  end else if(rcounter_reg[0]==1'b1)begin
       ad0 <= SDATA;
end
end

always@(negedge RST or posedge CLK )//or posedge rcounter_reg[1])
begin if(RST ==1'b0)begin
  ad1 <=1'b0;
  end else if(rcounter_reg[1]==1'b1)begin
       ad1 <= SDATA;
end
end

always@(negedge RST or posedge CLK )//or posedge rcounter_reg[2])
begin if(RST ==1'b0)begin
  ad2 <=1'b0;
  end else if(rcounter_reg[2]==1'b1)begin
  ad2 <= SDATA;
end
end

always@(negedge RST or posedge CLK )//or posedge rcounter_reg[3])
begin if(RST ==1'b0)begin
  ad3 <=1'b0;
  end else if(rcounter_reg[3]==1'b1)begin
    ad3 <= SDATA;
end
end

always@(negedge RST or posedge CLK )//or posedge rcounter_reg[4])
begin if(RST ==1'b0)begin
  ad4 <=1'b0;
  end else if(rcounter_reg[4]==1'b1)begin
   ad4 <= SDATA;
end
end

always@(negedge RST or posedge CLK )//or posedge rcounter_reg[5])
begin if(RST ==1'b0)begin
  ad5 <=1'b0;
  end else if(rcounter_reg[5]==1'b1)begin
   ad5 <= SDATA;
end
end

always@(negedge RST or posedge CLK )//or posedge rcounter_reg[6])
begin if(RST ==1'b0)begin
  ad6 <=1'b0;
  end else if(rcounter_reg[6]==1'b1)begin
   ad6 <= SDATA;
end
end

 always@(negedge RST or posedge CLK )//or posedge rcounter_reg[7])
begin if(RST ==1'b0)begin
  ad7 <=1'b0;
  end else if(rcounter_reg[7]==1'b1)begin
   ad7 <= SDATA;
end
end


 always@(negedge RST or posedge CLK )
begin if(RST ==1'b0)begin
  ad <=8'h0;
	end else if (CS_N == 1'b1)begin
	ad <=8'h0;
  end else if(rcounter_reg[7]==1'b1)begin
      ad <={ad0,ad1,ad2,ad3,ad4,ad5,ad6,SDATA};
end
end


always@(negedge RST or posedge CLK)
 begin if(RST ==1'b0)begin
  ld <=8'h0;
	end else if(wrcyc ==1'b1)begin
   ld <= ld +1 ;
	 ld1 <= ld;
	 ld2 <= ld >> 4;
end
end

assign WCYC_COUNTER = ld;

   
  always@(posedge SHIFT_CLK or  negedge RST)begin
  if(RST == 1'b0 )begin
	  enable_seg <= 2'b00;
 end else begin
   enable_seg <= enable_seg +1'b1;
	end
end




 
 always@* //* whenever inputs change,  holding counter value as the resister "SEVEN_SEG_DATA"
 begin
 case(enable_seg)
	2'b00:  SEVEN_SEG_DATA <= ~seven_seg4_hold;
	2'b01:  SEVEN_SEG_DATA<=~seven_seg1_hold;
  2'b10:  SEVEN_SEG_DATA<=~seven_seg2_hold;
  2'b11:  SEVEN_SEG_DATA<=~seven_seg3_hold;
	default SEVEN_SEG_DATA<=8'b11111111;
		endcase
	end
 
 always@(negedge RST or posedge SHIFT_CLK)
	 begin if(RST == 1'b0 )begin
	  dsel <= dselinit_value;
	  end else begin
    dsel[2]<=dsel[1]	;	//シフト動作を開始する
    dsel[1] <= dsel[2]	;	//シフト動作を開始する
   end
end
 
 assign DSEL[2:1] =~dsel[2:1];


always@(negedge RST or posedge wrcyc or posedge CLK)
begin if(RST ==1'b0)begin
 dseven_seg1_hold <=8'b01011011;
 end else if(wrcyc == 1'b1 )begin
 	case(ld2)
	4'b0000 : dseven_seg1_hold<= 8'b00111111 ; //'0'    dot   g   f    e    d    c    b    a
	4'b0001 : dseven_seg1_hold <= 8'b00000110 ; //'1'
	4'b0010 : dseven_seg1_hold<= 8'b01011011 ; //'2'
	4'b0011 : dseven_seg1_hold <= 8'b01001111 ; //'3'
	4'b0100 : dseven_seg1_hold <= 8'b01100110 ; //'4'
	4'b0101 : dseven_seg1_hold <= 8'b01101101 ; //'5'
	4'b0110 : dseven_seg1_hold <= 8'b01111101 ; //'6'
	4'b0111 : dseven_seg1_hold <= 8'b00100111 ; //'7'
	4'b1000 : dseven_seg1_hold <= 8'b01111111 ; //'8'
	4'b1001 : dseven_seg1_hold <= 8'b01101111 ; //'9'
	4'b1010 : dseven_seg1_hold <= 8'b01110111 ; //'A'
	4'b1011 : dseven_seg1_hold <= 8'b01111100 ; //'b'
	4'b1100 : dseven_seg1_hold <= 8'b00111001 ; //'c'
	4'b1101 : dseven_seg1_hold <= 8'b01011110 ; //'d'
	4'b1110 : dseven_seg1_hold <= 8'b01111001 ; //'E'
	4'b1111 : dseven_seg1_hold <= 8'b01110001 ; //'F'
	default: dseven_seg1_hold <= 8'b01110001;
	endcase
	end
	end
	
always@(negedge RST or posedge wrcyc or posedge CLK)
begin if(RST ==1'b0)begin
dseven_seg2_hold <=8'b00000110;
 end else if(wrcyc == 1'b1)begin
 	case(ld1)
	4'b0000 : dseven_seg2_hold<= 8'b00111111 ; //'0
	4'b0001 : dseven_seg2_hold <= 8'b00000110 ; //'1'
	4'b0010 : dseven_seg2_hold<= 8'b01011011 ; //'2'
	4'b0011 : dseven_seg2_hold <= 8'b01001111 ; //'3'
	4'b0100 : dseven_seg2_hold <= 8'b01100110 ; //'4'
	4'b0101 : dseven_seg2_hold <= 8'b01101101 ; //'5'
	4'b0110 : dseven_seg2_hold <= 8'b01111101 ; //'6'
	4'b0111 : dseven_seg2_hold <= 8'b00100111 ; //'7'
	4'b1000 : dseven_seg2_hold <= 8'b01111111 ; //'8'
	4'b1001 : dseven_seg2_hold <= 8'b01101111 ; //'9'
	4'b1010 : dseven_seg2_hold <= 8'b01110111 ; //'A'
	4'b1011 : dseven_seg2_hold <= 8'b01111100 ; //'b'
	4'b1100 : dseven_seg2_hold <= 8'b00111001  ; //'c'
	4'b1101 : dseven_seg2_hold <= 8'b01011110 ; //'d'
	4'b1110 : dseven_seg2_hold <= 8'b01111001 ; //'E'
	4'b1111 : dseven_seg2_hold <= 8'b01110001 ; //'F'
	 default: dseven_seg2_hold <= 8'b01110001;
	endcase
	end
	end
	
  always@(posedge SHIFT_CLK or  negedge RST)begin
  if(RST == 1'b0 )begin
	  denable_seg <= 1'b0;
 end else begin
    denable_seg <= denable_seg +1'b1;
	end
end

 always@* //* whenever inputs change,  holding counter value as the resister "SEVEN_SEG_DATA"
	begin
  case(denable_seg)
	1'b0:  DSEVEN_SEG_DATA <= ~dseven_seg2_hold;
	1'b1:  DSEVEN_SEG_DATA<=~dseven_seg1_hold;
	default DSEVEN_SEG_DATA<=8'b11111111;
	endcase
	end

 
 endmodule
 

***&color(#0066cc,white){&size(20){''1-4.テストベンチコード''};}; [#yec7ae8e]
`timescale 1 ns/ 1 ns
 module SPI_read1_vlg_tst();
 // constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg CLK;
reg SDATA;
reg RST;
reg CS_N; 
 reg RXD;
 reg CTS;
 reg SEND_SW;

 // wires           
wire COMOUT;
wire [2:1]  DSEL;
wire [7:0]  DSEVEN_SEG_DATA;
wire SCK2;
wire [4:1]  SEL;
wire [7:0]  SEVEN_SEG_DATA;
wire WRCYC;
wire [7:0] rdat;
//wire [7:0] POSTDATA;
      wire SHIFT_CLK;
		 wire SEC_CLK;
	    wire[7:0] LED_OUT;
		 wire[7:0] RDAT;
		 wire TXD;
		 wire RTS;
		 wire SEND_BUSY;
		 wire SEND_START_OUT;

parameter STEP1 = 500;    // ns
parameter STEP2 = 10;	//ns  33MHz
 
// assign statements (if any)                          
SPI_read1 i1 (
// port map - connection between master ports and signals/registers   
	.CLK(CLK),
	.COMOUT(COMOUT),
	.DSEL(DSEL),
	.DSEVEN_SEG_DATA(DSEVEN_SEG_DATA),
	.SDATA(SDATA),
	.CS_N(CS_N),
	.RST(RST),
	.SHIFT_CLK(SHIFT_CLK),
	.SEC_CLK(SEC_CLK),
	.SEL(SEL),
	.SEVEN_SEG_DATA(SEVEN_SEG_DATA),
	.WRCYC(WRCYC),
	//.POSTDATA(POSTDATA),
	.RDAT(RDAT),
	.EN80(EN80),
	.LED_OUT(LED_OUT),
	.TXD(TXD),
	.RTS(RTS),
	.SEND_BUSY(SEND_BUSY),
	.RXD(RXD),
  .CTS(CTS),
  .SEND_SW(SEND_SW),
	.SEND_START_OUT(SEND_START_OUT)

);

initial                                                
begin           
RST <=1'b0;   
CLK <=1'b0; 
CS_N <= 1'b1;  

 //1

//RST deassert CS_N(frame) assert  addr 80h data 5Ah
#10
#0 SDATA<=4'b0000;  //1 start
#10 CS_N <= 1'b0;
#0 RST <= 1'b1;
//#19 CS_N <=1'b1;
#0 SDATA<=1'b1;  //    2 
#10 SDATA<=1'b0;//0x0  3 
#10 SDATA<=1'b1;//0x0  4 
#10 SDATA<=1'b0;//0x8  5 
#10 SDATA<=1'b1;//0x0  6 
#10 SDATA<=1'b0;//0xA  7 
#10 SDATA<=1'b1;//0x5  8 
#10 SDATA<=1'b0;//0x1  9 
#10 CS_N <= 1'b1;
  
 #10 CS_N <= 1'b0;
 #0 SDATA<=1'b0;  //    2 
#10 SDATA<=1'b0;//0x0  3 
#10 SDATA<=1'b0;//0x0  4 
#10 SDATA<=1'b0;//0x8  5 
#10 SDATA<=1'b1;//0x0  6 
#10 SDATA<=1'b0;//0xA  7 
#10 SDATA<=1'b0;//0x5  8 
#10 SDATA<=1'b0;//0x1  9 
#10 CS_N <= 1'b1;
  
  #10 CS_N <= 1'b0;
 #0 SDATA<=1'b0;  //    2 
#10 SDATA<=1'b0;//0x0  3 
#10 SDATA<=1'b0;//0x0  4 
#10 SDATA<=1'b0;//0x8  5 
#10 SDATA<=1'b1;//0x0  6 
#10 SDATA<=1'b0;//0xA  7 
#10 SDATA<=1'b0;//0x5  8 
#10 SDATA<=1'b0;//0x1  9 
#10 CS_N <= 1'b1;
  
	  #10 CS_N <= 1'b0;
 #0 SDATA<=1'b0;  //    2 
#10 SDATA<=1'b0;//0x0  3 
#10 SDATA<=1'b0;//0x0  4 
#10 SDATA<=1'b1;//0x8  5 
#10 SDATA<=1'b1;//0x0  6 
#10 SDATA<=1'b0;//0xA  7 
#10 SDATA<=1'b0;//0x5  8 
#10 SDATA<=1'b0;//0x1  9 
#10 CS_N <= 1'b1;
  #10
	
  #10 CS_N <= 1'b0;
 #0 SDATA<=1'b0;  //    2 
#10 SDATA<=1'b0;//0x0  3 
#10 SDATA<=1'b0;//0x0  4 
#10 SDATA<=1'b0;//0x8  5 
#10 SDATA<=1'b1;//0x0  6 
#10 SDATA<=1'b0;//0xA  7 
#10 SDATA<=1'b0;//0x5  8 
#10 SDATA<=1'b0;//0x1  9 
#10 CS_N <= 1'b1;
  #10

$display("Running testbench");                       
end  
                                                 
//always#(STEP1/2)
//begin
//RST <= ~RST;
//end

always#(STEP2/2)
begin
CLK <= ~CLK;
end                                           
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
//begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
//@eachvec;                                              
// --> end                                             
//end     
                                               
endmodule