1.PWM_SYNC2
1-1.仕様(Specification)
1-2.タイミングチャート(timingchart)
1-3.回路図 circuit diagram
1-4-1.ピン一覧_全体
1-4-2.ピン一覧_Evaluation Bard
2.ソースコード(source code)
3.テストベンチソースコード(test bench source code)
4.タイミングコンストレインソースコード(constrain file)
5.結果(result)
目的:同期DCDCコンバーターのUGATE、LGATEをDEADTIME付で生成。
(1)構成概略
主デバイス:
MAX10 10M08SAE144I7G LogicElements8k, SpeedGrade7(rising rate 2nsec)
By using Evaluation Bard "EK-10M08E144ES/P
#ref(): File not found: "kousei1.png" at page "verilog/PWM_SYNC2"
(2)仕様
入力:50MHz 周波数:330kHz(固定) 内部クロック:100MHz(50MHz-2逓倍 FPGA内蔵PLLを使用) PWM分解能:約10nsec Deadtime:同上(内部クロック同期 10nsec刻みで0nsec~80nsecで設定可能)~ Duty(UGATEオン):0/303~ 255/303 (0~約84.1%)
省略
Please reffer to the Schematic of Evaluation Bard "EK-10M08E144ES/P"
Abbreviation
・Pin Assignment
CLK | Input | PIN_27 | 2 | B2_N0 | PIN_27 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
DTIME[2] | Input | PIN_59 | 3 | B3_N0 | PIN_59 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
DTIME[1] | Input | PIN_57 | 3 | B3_N0 | PIN_57 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
DTIME[0] | Input | PIN_56 | 3 | B3_N0 | PIN_56 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
LGATE | Output | PIN_46 | 3 | B3_N0 | PIN_46 | 3.3-V LVTTL | 8mA (default) | 2 (default) | |||
LOCKED_OUT | Output | PIN_29 | 2 | B2_N0 | PIN_29 | 3.3-V LVTTL | 8mA (default) | 2 (default) | |||
PW[7] | Input | PIN_86 | 5 | B5_N0 | PIN_86 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
PW[6] | Input | PIN_84 | 5 | B5_N0 | PIN_84 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
PW[5] | Input | PIN_81 | 5 | B5_N0 | PIN_81 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
PW[4] | Input | PIN_79 | 5 | B5_N0 | PIN_79 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
PW[3] | Input | PIN_77 | 5 | B5_N0 | PIN_77 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
PW[2] | Input | PIN_76 | 5 | B5_N0 | PIN_76 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
PW[1] | Input | PIN_75 | 5 | B5_N0 | PIN_75 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
PW[0] | Input | PIN_74 | 5 | B5_N0 | PIN_74 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
RES_n | Input | PIN_44 | 3 | B3_N0 | PIN_44 | 3.3 V Schmitt Trigger | 8mA (default) | ||||
UGATE | Output | PIN_32 | 2 | B2_N0 | PIN_32 | 3.3-V LVTTL | 8mA (default) | 2 (default) | |||
LED_out[0] | Unknown | PIN_132 | 8 | B8_N0 | 3.3-V LVTTL (default) | 8mA (default) | |||||
LED_out[1] | Unknown | PIN_134 | 8 | B8_N0 | 3.3-V LVTTL (default) | 8mA (default) | |||||
LED_out[2] | Unknown | PIN_135 | 8 | B8_N0 | 3.3-V LVTTL (default) | 8mA (default) | |||||
LED_out[3] | Unknown | PIN_140 | 8 | B8_N0 | 3.3-V LVTTL (default) | 8mA (default) | |||||
LED_out[4] | Unknown | PIN_141 | 8 | B8_N0 | 3.3-V LVTTL (default) | 8mA (default) |
//1/26 worked// module PWM_SYNC2( CLK, RES_n, DTIME, PW, UGATE, LGATE, LOCKED_OUT ); /******input definition****************/ input CLK; input RES_n; input [2:0] DTIME; input [7:0] PW; /******output definition****************/ output UGATE; output LGATE; output LOCKED_OUT; /******register****************/ reg [11:0] cnt; reg pout; reg [2:0]deadtime_reg; reg deadtime_en; reg lgate_en_start_flag; wire hclk; wire RES_p; wire hlocked; initial deadtime_reg = 3'b000 ; initial cnt = 12'h000; initial lgate_en_start_flag = 1'b0; // parameter F330k_cnt1=8'h97; //330kHz at 50MHz parameter F330k_cnt1=12'h12f; //330kHz at 100MHz pll U0( .areset(RES_P), .inclk0(CLK), .c0(hclk), .locked(hlocked) ); assign RES_P = ~RES_n; assign LOCKEDOUT = hlocked; //always@(negedge RES_n or posedge CLK) always@(negedge RES_n or posedge hclk) begin if(!RES_n)begin pout <=0; cnt <=0; deadtime_en <=0; deadtime_reg <=3'b000; end else if(cnt == F330k_cnt1)begin cnt <= 12'h000; deadtime_en <= 1'b0; deadtime_reg <= 3'b000; end else begin cnt <= cnt + 1; deadtime_reg <= deadtime_reg + 1; deadtime_en <= (DTIME > deadtime_reg & cnt < 12'b000000001000); pout <= (PW >= cnt ); lgate_en_start_flag <= (PW >= cnt - DTIME); end end assign UGATE = pout ^ deadtime_en; assign LGATE = ~(pout | lgate_en_start_flag); endmodule
`timescale 1 ns/ 1 ns module PWM_SYNC2_vlg_tst(); // constants // general purpose registers reg eachvec; // test vector input registers reg CLK; reg RES_n; reg [2:0] DTIME; reg [7:0] PW; // wires (Output) wire UGATE; wire LGATE; wire LOCKED_OUT; parameter STEP1 = 500; // ns parameter STEP2 = 20; //ns 50MHz //Lower Layer Port connection pll U0(.areset(RES_n),.inclk0(CLK),.c0(hclk),.locked(hlocked)); //Initial Description initial begin RES_n <=1'b0; CLK <=1'b0; //Test Bench #0 DTIME<=3'b001; #0 PW<=8'h1b; #10 #100 RES_n <= 1'b1; #10000 #0 DTIME<=3'b010; #100 RES_n <= 1'b1; #1000 $display("Running testbench"); end always#(STEP2/2) begin CLK <= ~CLK ; end endmodule
下表に、実際に出力させてみたときの電圧値を示す。~
#ref(): File not found: "result1.png" at page "verilog/PWM_SYNC2"