verilog / PORT80h translator1_1_570

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1.PORT80h DECODER
1-1.仕様(Specification)
1-2.タイミングチャート(timingchart)
1-3.回路図 circuit diagram
1-4-1.ピン一覧_評価ボードAZMMAXVT1(pin assign evaluation board azmmaxvt1)
1-4-2.ピン一覧_CPLD_5M570ZT144C5N(pin assign CPLD_5M570ZT144C5N)
1-5.ソースコード(source code)
1-6.テストベンチソースコード(test bench source code)
1-7.タイミングコンストレインソースコード(constrain file)

1.PORT80h DECODER2 †

''1-1.仕様' †

x86系のBIOSポストコードを読めるデバイス。(The device which reads x86-BIOS POST CODE.)
入力：LPCバス
(Input:LPC I/F)
出力：ライトアドレス、PORT80hのデータ(バイナリデータをLED表示、および16進で7seg表示)
(Output:data at Port80h in the 7seg-display &LED)
ライトアドレスは、PORT80hに限らずすべてのライトサイクル中のアドレスを表示(動かないとつまらないため)

1-2.タイミングチャート(Timing chart) †

LPCバスからPORT80hを読み取るタイミングチャートは下記の通り。

1-3.回路図 †

CPLD MAX5は評価ボードAZMMAXVT1を使用する。
他下記の通り。

''1-4-1.ピン一覧 評価ボードAZMMAXVT1' †

1-4-2.ピン一覧_CPLD †

1-5.ソースコード †

   module LPC_PORT80h_translator1(
CLK, //standard clock
RST,//RST Input
LADCOM,//LAD Input,
NFRAME,//Manual Input or NFRAME
COMOUT,
SCK2,
WRCYC,
SEVEN_SEG_DATA,
SEL,
DSEL,
DSEVEN_SEG_DATA,
POSTDATA,
EN80
 	);
	
// input definition LPCBUS//
	input CLK;
	input RST;
	input[3:0] LADCOM;
 	input NFRAME;
//output definition//
	output  SCK2;
	output COMOUT;
	output reg WRCYC; 
	output [4:1] SEL;
	output reg[7:0] SEVEN_SEG_DATA;
  output [2:1] DSEL;
	output reg[7:0] DSEVEN_SEG_DATA;
	output[7:0] POSTDATA;
	output EN80;
// register//
	reg [15:0] sec_cnt2 ;
  reg  sec1_flag2 ;
  reg  toggle_flag2 ; 
	reg[11:0] rcounter_reg;
	reg com_reg;
	reg nframe;
	wire COMOUT;
	reg Wrcyc;
	reg[7:0] seven_seg1_hold;
	reg[7:0] seven_seg2_hold;
	reg[7:0] seven_seg3_hold;
	reg[7:0] seven_seg4_hold;
	reg[7:0] seven_seg_data;
	reg[4:1]sel;
	reg[1:0]enable_seg;
	reg[2:1]dsel;
	reg denable_seg;
	reg[7:0] dseven_seg1_hold;
	reg[7:0] dseven_seg2_hold;
	reg[4:0] cs_counter;
 	reg[3:0] ad1;
  reg[3:0] ad2;
	reg[3:0] ad3;
	reg[3:0] ad4;
	reg[15:0] ad;
	reg en80;
	reg[3:0] ld1;
	reg[3:0] ld2;
	reg[7:0] ld;
	reg startflag;
 //***parameter definition***//
 //parameter F33M0000_cnt2=16'h35B6 ; //High time 0.00416667sec 2400bps
   parameter F33M0000_cnt2=16'h0d6d ; //d6dh High time 0.00005208sec 9600bps
 //parameter F33M0000_cnt2=16'h011E ; //High time 0.00000868sec 115.2kbps
 parameter	selinit_value = 4'b0001	;
 parameter dselinit_value =2'b01;
 parameter ld1init_value =4'b1111;
 parameter ld2init_value =4'b1111;
 parameter rcounter_reg_init_value = 12'b100000000000;
 initial	cs_counter = 5'b00000;
 initial   nframe <= 1'b1 ;
 //***7seg Dynamic lighting SCK2 generation***//
always@(posedge CLK)
begin
  if(sec_cnt2 == F33M0000_cnt2) begin
	  sec_cnt2 <= 16'h0000 ; //counter counting up to the parameter
	  sec1_flag2 <= 1'b1; 
	end else begin
	  sec_cnt2 <= sec_cnt2 + 1 ;
	  sec1_flag2 <= 1'b0 ;
	end
end

always@(posedge CLK)
begin
  if(sec1_flag2 == 1'b1 )begin
	 toggle_flag2 <= !toggle_flag2 ;
	end
end

assign SCK2 =!toggle_flag2;

// ***RING COUNTER***//
/*
always@(posedge CLK or negedge RST  or posedge nframe)
begin
  if(RST == 1'b0 ) begin
	   rcounter_reg <= 12'b000000000000 ;
	end else if(nframe ==1'b1)begin//1'b1
	   rcounter_reg <= 12'b000000000000 ;
	end else begin
	    rcounter_reg <=  rcounter_reg <<1;
		 rcounter_reg [0] <= rcounter[11];
	end
end

always@*
begin
      rcounter[11] <= ~|rcounter_reg;//16
		 rcounter[10:0]<=rcounter_reg;
 end
 */

always@(posedge CLK or negedge RST  or posedge nframe)
begin
  if(RST == 1'b0 ) begin
	   rcounter_reg <= 12'b000000000001 ;
	end else if(nframe ==1'b1)begin
	   rcounter_reg <= 12'b000000000001 ;
	end else begin
		rcounter_reg <= {rcounter_reg,rcounter_reg[11]};
	end
end

always@(posedge CLK or  negedge RST or negedge NFRAME)
 begin
  if(RST == 1'b0 )begin
	   cs_counter<= 5'b00000;
	end else if(NFRAME == 1'b0)begin	
		cs_counter <=5'b00000;
  end else if(cs_counter > 5'b10001)begin
  cs_counter <=5'b00000;
	end else begin
   cs_counter <= cs_counter +1'b1;
	end
end

always@*
 begin
 if(RST == 1'b0)begin
   nframe<= 1'b1;
 end else if(NFRAME ==1'b0)begin
  nframe <= 1'b1;
 end else if(cs_counter >5'b01011)begin
  nframe <=1'b1;
 end else begin
  nframe <=1'b0;
 end
 end
   
always@(negedge RST or posedge CLK)
begin
if(RST == 1'b0)begin
  startflag <=1'b0;
end else if(NFRAME == 1'b0) 
begin
	 startflag <= 1'b1;
end else begin
   startflag <= 1'b0;
	end
end
  
always@( negedge RST or negedge NFRAME or posedge LADCOM[3:0] or  posedge CLK or posedge startflag )
begin if(RST ==1'b0)begin
 com_reg <=1'b0;
    end else if(startflag ==1'b1 )begin
	  	case(LADCOM)
	4'b0000 : com_reg <= 1'b0 ; 
	4'b0001 : com_reg <= 1'b0 ;
	4'b0010 : com_reg <= 1'b1 ;
	4'b0011 : com_reg <= 1'b0 ; 
	4'b0100 : com_reg <= 1'b0 ;
	4'b0101 : com_reg <= 1'b0 ;
	4'b0110 : com_reg <= 1'b0 ; 
	4'b0111 : com_reg <= 1'b0 ;
	4'b1000 : com_reg <= 1'b0 ;
	4'b1001 : com_reg <= 1'b0 ;
	4'b1010 : com_reg <= 1'b0 ; 
	4'b1011 : com_reg <= 1'b0 ;
	4'b1100 : com_reg <= 1'b0 ;
	4'b1101 : com_reg <= 1'b0 ;
	4'b1110 : com_reg <= 1'b0 ;
	4'b1111 : com_reg <= 1'b0 ; 
	default:  com_reg <= 1'b0 ; 
	endcase
	end
	end
   
assign COMOUT =com_reg;
	 
always@( negedge RST or negedge NFRAME or posedge LADCOM[3:0] or  posedge CLK or posedge startflag)
begin if(RST ==1'b0)begin
 Wrcyc <=1'b0;
    end else if(startflag ==1'b1 )begin
	  	case(LADCOM)
	4'b0000 : Wrcyc <= 1'b0 ; 
	4'b0001 : Wrcyc <= 1'b0 ; 
	4'b0010 : Wrcyc <= 1'b1 ; 
	4'b0011 : Wrcyc <= 1'b0 ; 
	4'b0100 : Wrcyc <= 1'b0 ;
	4'b0101 : Wrcyc <= 1'b0 ;
	4'b0110 : Wrcyc <= 1'b0 ; 
	4'b0111 : Wrcyc <= 1'b0 ;
	4'b1000 : Wrcyc <= 1'b0 ;
	4'b1001 : Wrcyc <= 1'b0 ;
	4'b1010 : Wrcyc <= 1'b0 ; 
	4'b1011 : Wrcyc <= 1'b0 ;
	4'b1100 : Wrcyc <= 1'b0 ;
	4'b1101 : Wrcyc <= 1'b0 ;
	4'b1110 : Wrcyc <= 1'b0 ;
	4'b1111 : Wrcyc <= 1'b0 ; 
	default:  Wrcyc <= 1'b0 ; 
	endcase
	end
	end

always@(posedge Wrcyc or negedge NFRAME)
	begin if(NFRAME ==1'b0)begin
	WRCYC <=1'b0;
	end else begin
	WRCYC <= ~nframe;
	end
	end
 
always@(posedge SCK2 or  negedge RST)begin
  if(RST == 1'b0 )begin
	  sel <= selinit_value;
	  end else begin
   sel[4] <= sel[1]	;	//シフト動作を開始する
 sel[3] <= sel[4]	;	//シフト動作を開始する
 sel[2] <= sel[3]	;	//シフト動作を開始する
 sel[1] <= sel[2]	;
   end
end

assign SEL[4:1] = ~sel[4:1];

always@(negedge RST or posedge CLK or posedge rcounter_reg[1])
begin if(RST ==1'b0)begin
 seven_seg1_hold <=8'b00000110;
 end else begin
	 if( rcounter_reg[1]==1'b1)
	  	case(ad1)
	4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0'    dot   g   f    e    d    c    b    a
	4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg1_hold <= 8'b00111001 ; //'c'
	4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F'
	default: seven_seg1_hold <= 8'b01110001;
	endcase
	end
	end
	
always@(negedge RST or posedge CLK or posedge rcounter_reg[2])
begin if(RST ==1'b0)begin
  seven_seg2_hold <=8'b01011011;
    end else begin
	  if(rcounter_reg[2]==1'b1)
		  	case(ad2)
	4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0
	4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg2_hold <= 8'b00111001 ; //'c'
	4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F'
	 default: seven_seg2_hold <= 8'b01110001;
	endcase
	end
	end
	
always@(negedge RST or posedge CLK or posedge rcounter_reg[3] )
 begin if(RST ==1'b0)begin
  seven_seg3_hold <=8'b01001111;
  end else begin 
	 if(rcounter_reg[3]==1'b1)
	case(ad3)
	4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0'
	4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg3_hold <= 8'b00111001 ; //'c'
	4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F'
  default: seven_seg3_hold <= 8'b01110001;
	endcase
	end
	end

always@(negedge RST or posedge CLK or posedge rcounter_reg[4])	
begin if(RST ==1'b0)begin
 seven_seg4_hold <=8'b01100110;
  end else begin   
	 if(rcounter_reg[4]==1'b1)
	 	case(ad4)
	4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0'
	4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg4_hold <= 8'b00111001 ; //'c'
	4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F'
	  default: seven_seg4_hold <= 8'b01110001;
	endcase
end
end

always@(negedge RST or posedge CLK or posedge rcounter_reg[1])
begin if(RST ==1'b0)begin
  ad1 <=4'b0000;
  end else if(rcounter_reg[1]==1'b1)begin
    if(WRCYC==1'b1)
  ad1 <= LADCOM;
end
end

always@(negedge RST or posedge CLK or posedge rcounter_reg[2])
begin if(RST ==1'b0)begin
  ad2 <=4'b0000;
  end else if(rcounter_reg[2]==1'b1)begin
    if(WRCYC==1'b1)
  ad2 <= LADCOM;
end
end

always@(negedge RST or posedge CLK or posedge rcounter_reg[3])
begin if(RST ==1'b0)begin
  ad3 <=4'b0000;
  end else if(rcounter_reg[3]==1'b1)begin
    if(WRCYC==1'b1)
  ad3 <= LADCOM;
end
end

always@(negedge RST or posedge CLK or posedge rcounter_reg[4])
begin if(RST ==1'b0)begin
  ad4 <=4'b0000;
  end else if(rcounter_reg[4]==1'b1)begin
    if(WRCYC==1'b1)
  ad4 <= LADCOM;
end
end


 always@(negedge RST or posedge CLK or posedge rcounter_reg[5])
begin if(RST ==1'b0)begin
  ad <=16'h0000;
  end else if(rcounter_reg[5]==1'b1)begin
    if(WRCYC==1'b1)
  ad <={ad1,ad2,ad3,ad4};
end
end


always@(negedge RST or posedge CLK or posedge rcounter_reg[6])
begin if(RST ==1'b0)begin
  ld1 <=4'b0000;
  end else if(rcounter_reg[6]==1'b1)begin
    if(WRCYC==1'b1)
  ld1 <= LADCOM;
end
end

always@(negedge RST or posedge CLK or posedge rcounter_reg[5])
begin if(RST ==1'b0)begin
  ld2 <=4'b0000;
  end else if(rcounter_reg[5]==1'b1)begin
    if(WRCYC==1'b1 )
  ld2 <=LADCOM;
end
end

 always@(negedge RST or posedge CLK  or posedge EN80)
begin if(RST ==1'b0)begin
  ld <=8'b00000000;
  end else if(EN80==1'b1)begin
  ld <={ld1,ld2};
end
end

assign POSTDATA = ld;

always@(negedge RST or negedge NFRAME or posedge CLK )
 begin if(RST ==1'b0)begin
  en80 <=1'b0;
	end else if(NFRAME==1'b0)begin
	en80 <=1'b0;
  end else if(WRCYC==1'b1 && ad == 16'h0080)begin
  en80<=1'b1;
	end else begin
	en80<=1'b0;
end
end

assign EN80 = en80&rcounter_reg[7];
   
  always@(posedge SCK2 or  negedge RST)begin
  if(RST == 1'b0 )begin
	  enable_seg <= 2'b00;
 end else begin
   enable_seg <= enable_seg +1'b1;
	end
end
 
 always@* //* whenever inputs change,  holding counter value as the resister "SEVEN_SEG_DATA"
 begin
 case(enable_seg)
	2'b00:  SEVEN_SEG_DATA <= ~seven_seg4_hold;
	2'b01:  SEVEN_SEG_DATA<=~seven_seg1_hold;
  2'b10:  SEVEN_SEG_DATA<=~seven_seg2_hold;
  2'b11:  SEVEN_SEG_DATA<=~seven_seg3_hold;
	default SEVEN_SEG_DATA<=8'b11111111;
		endcase
	end
 
 always@(negedge RST or posedge SCK2)
	 begin if(RST == 1'b0 )begin
	  dsel <= dselinit_value;
	  end else begin
    dsel[2]<=dsel[1]	;	//シフト動作を開始する
    dsel[1] <= dsel[2]	;	//シフト動作を開始する
   end
end
 
 assign DSEL[2:1] =~dsel[2:1];

always@(negedge RST or posedge EN80 or posedge CLK)
begin if(RST ==1'b0)begin
 dseven_seg1_hold <=8'b01011011;
 end else if(EN80 == 1'b1 )begin
 	case(ld2)
	4'b0000 : dseven_seg1_hold<= 8'b00111111 ; //'0'    dot   g   f    e    d    c    b    a
	4'b0001 : dseven_seg1_hold <= 8'b00000110 ; //'1'
	4'b0010 : dseven_seg1_hold<= 8'b01011011 ; //'2'
	4'b0011 : dseven_seg1_hold <= 8'b01001111 ; //'3'
	4'b0100 : dseven_seg1_hold <= 8'b01100110 ; //'4'
	4'b0101 : dseven_seg1_hold <= 8'b01101101 ; //'5'
	4'b0110 : dseven_seg1_hold <= 8'b01111101 ; //'6'
	4'b0111 : dseven_seg1_hold <= 8'b00100111 ; //'7'
	4'b1000 : dseven_seg1_hold <= 8'b01111111 ; //'8'
	4'b1001 : dseven_seg1_hold <= 8'b01101111 ; //'9'
	4'b1010 : dseven_seg1_hold <= 8'b01110111 ; //'A'
	4'b1011 : dseven_seg1_hold <= 8'b01111100 ; //'b'
	4'b1100 : dseven_seg1_hold <= 8'b00111001 ; //'c'
	4'b1101 : dseven_seg1_hold <= 8'b01011110 ; //'d'
	4'b1110 : dseven_seg1_hold <= 8'b01111001 ; //'E'
	4'b1111 : dseven_seg1_hold <= 8'b01110001 ; //'F'
	default: dseven_seg1_hold <= 8'b01110001;
	endcase
	end
	end
	
always@(negedge RST or posedge EN80 or posedge CLK)
begin if(RST ==1'b0)begin
dseven_seg2_hold <=8'b00000110;
 end else if(EN80 == 1'b1)begin
 	case(ld1)
	4'b0000 : dseven_seg2_hold<= 8'b00111111 ; //'0
	4'b0001 : dseven_seg2_hold <= 8'b00000110 ; //'1'
	4'b0010 : dseven_seg2_hold<= 8'b01011011 ; //'2'
	4'b0011 : dseven_seg2_hold <= 8'b01001111 ; //'3'
	4'b0100 : dseven_seg2_hold <= 8'b01100110 ; //'4'
	4'b0101 : dseven_seg2_hold <= 8'b01101101 ; //'5'
	4'b0110 : dseven_seg2_hold <= 8'b01111101 ; //'6'
	4'b0111 : dseven_seg2_hold <= 8'b00100111 ; //'7'
	4'b1000 : dseven_seg2_hold <= 8'b01111111 ; //'8'
	4'b1001 : dseven_seg2_hold <= 8'b01101111 ; //'9'
	4'b1010 : dseven_seg2_hold <= 8'b01110111 ; //'A'
	4'b1011 : dseven_seg2_hold <= 8'b01111100 ; //'b'
	4'b1100 : dseven_seg2_hold <= 8'b00111001  ; //'c'
	4'b1101 : dseven_seg2_hold <= 8'b01011110 ; //'d'
	4'b1110 : dseven_seg2_hold <= 8'b01111001 ; //'E'
	4'b1111 : dseven_seg2_hold <= 8'b01110001 ; //'F'
	 default: dseven_seg2_hold <= 8'b01110001;
	endcase
	end
	end
	
  always@(posedge SCK2 or  negedge RST)begin
  if(RST == 1'b0 )begin
	  denable_seg <= 1'b0;
 end else begin
    denable_seg <= denable_seg +1'b1;
	end
end

 always@* //* whenever inputs change,  holding counter value as the resister "SEVEN_SEG_DATA"
	begin
  case(denable_seg)
	1'b0:  DSEVEN_SEG_DATA <= ~dseven_seg2_hold;
	1'b1:  DSEVEN_SEG_DATA<=~dseven_seg1_hold;
	default DSEVEN_SEG_DATA<=8'b11111111;
	endcase
	end
 
 endmodule
    

1-6.テストベンチコード †

`timescale 1 ns/ 1 ns
module LPC_PORT80h_translator1_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg CLK;
reg [3:0] LADCOM;
reg RST;
reg NFRAME; 
 // wires           
wire COMOUT;
wire [2:1]  DSEL;
wire [7:0]  DSEVEN_SEG_DATA;
wire SCK2;
wire [4:1]  SEL;
wire [7:0]  SEVEN_SEG_DATA;
wire WRCYC;
wire [7:0] POSTDATA;

parameter STEP1 = 500;    // ns
parameter STEP2 = 10;	//ns  33MHz
 
// assign statements (if any)                          
LPC_PORT80h_translator1 i1 (
// port map - connection between master ports and signals/registers   
	.CLK(CLK),
	.COMOUT(COMOUT),
	.DSEL(DSEL),
	.DSEVEN_SEG_DATA(DSEVEN_SEG_DATA),
	.LADCOM(LADCOM),
	.NFRAME(NFRAME),
	.RST(RST),
	.SCK2(SCK2),
	.SEL(SEL),
	.SEVEN_SEG_DATA(SEVEN_SEG_DATA),
	.WRCYC(WRCYC),
	.POSTDATA(POSTDATA),
	.EN80(EN80)

);

initial                                                
begin           
RST <=1'b0;   
CLK <=1'b0; 
NFRAME <= 1'b1;  
 //1

//RST deassert NFRAME(frame) assert  addr 80h data 5Ah
#0 LADCOM[3:0] <=4'b0000;  //1 start
#1 NFRAME <= 1'b0;
#0 RST <= 1'b1;
#9 NFRAME <=1'b1;
#0 LADCOM[3:0] <=4'b0010;  //    2 command
#10 LADCOM[3:0] <=4'b0000;//0x0  3 addr1
#10 LADCOM[3:0] <=4'b0000;//0x0  4 addr2
#10 LADCOM[3:0] <=4'b1000;//0x8  5 addr3
#10 LADCOM[3:0] <=4'b0000;//0x0  6 addr4
#10 LADCOM[3:0] <=4'b1010;//0xA  7 data1
#10 LADCOM[3:0] <=4'b0101;//0x5  8 data2
#10 LADCOM[3:0] <=4'b0001;//0x1  9 
#10 LADCOM[3:0] <=4'b0010;//0x2  10 
#10 LADCOM[3:0] <=4'b0100;//0x8  11
#10 LADCOM[3:0] <=4'b1111;//0xf  12
#10 LADCOM[3:0] <=4'b1101;//0xf  13
#10
//RST deassert NFRAME(frame) assert  addr f359h data 21h
#10 RST <= 1'b0;
#10 RST <= 1'b1;
#10 NFRAME <= 1'b0;
#0 LADCOM[3:0] <=4'b0000;  //0x0   1
#10 NFRAME <=1'b1;
#0 LADCOM[3:0] <=4'b0010;  //0x0   2
#10 LADCOM[3:0] <=4'b1111;//0xf    3 addr1
#10 LADCOM[3:0] <=4'b0011;//0x3    4 addr2
#10 LADCOM[3:0] <=4'b0101;//0x5    5 addr3
#10 LADCOM[3:0] <=4'b1001;//0x9    6 addr4
#10 LADCOM[3:0] <=4'b0000;//0x1    7 data1
#10 LADCOM[3:0] <=4'b0010;//0x2    8 data2
#10 LADCOM[3:0] <=4'b0001;//       9
#10 LADCOM[3:0] <=4'b0010;//      10 
#10 LADCOM[3:0] <=4'b0100;//      11
#10 LADCOM[3:0] <=4'b1111;//      12
 #10 LADCOM[3:0] <=4'b1101;//      13
 #10
 //NFRAME(frame) assert  addr 0081h data 76h
#10 NFRAME <= 1'b0;
#0 LADCOM[3:0] <=4'b0000;  //1
#10 NFRAME <=1'b1;
#0 LADCOM[3:0] <=4'b0000;  //0x0   command 0
#10 LADCOM[3:0] <=4'b0000;//0x1    addr1 0
#10 LADCOM[3:0] <=4'b1000;//0x2    addr2 8
#10 LADCOM[3:0] <=4'b0001;//0x4    addr3 1
#10 LADCOM[3:0] <=4'b1000;//0x8    addr4 6
#10 LADCOM[3:0] <=4'b0000;//0x1    data1 7
#10 LADCOM[3:0] <=4'b0010;//0x2    data2 8
#10 LADCOM[3:0] <=4'b0001;//       9
#10 LADCOM[3:0] <=4'b0010;//       10
#10 LADCOM[3:0] <=4'b0100;//       11
#10 LADCOM[3:0] <=4'b1111;//       12
#10 LADCOM[3:0] <=4'b1101;//       13
#10
  //NFRAME(frame) assert  addr 0080h data bah
#10 NFRAME <= 1'b0;
#0 LADCOM[3:0] <=4'b0000;      //     1
#10 NFRAME <=1'b1;
#0 LADCOM[3:0] <=4'b0010;  //0x2      2
#10 LADCOM[3:0] <=4'b0000;//0x0       3
#10 LADCOM[3:0] <=4'b0000;//0x0      4
#10 LADCOM[3:0] <=4'b1000;//0x8      5
#10 LADCOM[3:0] <=4'b0000;//0x0      6
#10 LADCOM[3:0] <=4'b1010;//0xa      7
#10 LADCOM[3:0] <=4'b1011;//0xb      8
#10 LADCOM[3:0] <=4'b1100;//0xc      9
#10 LADCOM[3:0] <=4'b1101;//0xd      10
#10 LADCOM[3:0] <=4'b1110;//0xe      11
#10 LADCOM[3:0] <=4'b1111;//0xf      12
#10 LADCOM[3:0] <=4'b1101;//0xf      13
// code that executes only once                        
// insert code here --> begin                          
                                                      
// --> end                                             
$display("Running testbench");                       
end  
                                                 
//always#(STEP1/2)
//begin
//RST <= ~RST;
//end

always#(STEP2/2)
begin
CLK <= ~CLK;
end                                           
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
//begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
                                                       
//@eachvec;                                              
// --> end                                             
//end     
                                               
endmodule

''1-7.タイミングコンストレインファイル" †

create_clock -name CLK -period 30.3 [get_keepers {CLK}]