verilog
・1 DAC_SPI †
module DAC_SPI(
CLK,
reset ,
SW1,
SW2,
CS,
seg7_n,
counter4,
counter5,
countera5,
SCK,
sck_out,
SDATA,
SOUT,
PRL_N
);
//******入出力******//
input CLK;
input reset ;
input SW1 ;
input SW2 ;
output CS ;
output[7:0] seg7_n ;
output[3:0] counter4 ;
output[4:0] counter5 ;
output[5:0] countera5 ;
output SCK ;
output sck_out ;
output[15:0] SDATA ;
output SOUT;
output[15:0] PRL_N ;
//******内部ノード******//
reg [31:0] sec_cnt ;//１秒作成用カウンタ
reg[3:0] reg_counter4 ; //ボタン入力回数
reg[4:0] reg_counter5 ;//16bit 1フレーム作成
reg[4:0] reg_countera5 ;
reg sw2_counter ;
reg frame ;//16bit 1フレームフラグ
reg sck ;//sckのcs lowのときのマスク
reg[7:0] reg_seg7 ;//7segへの出力バッファ
reg[15:0] prl_n ;
reg[15:0] sdata ;
reg sckmask ;
//******内部回路******//
//initial frame <= 1'b1 ;
//initial reg_counter5 <= 5'b00000 ;
//initial prl_n= 16'hF0F0 ;
//
//カウンタ部
//基準クロックカウンタ//
//parameter F33M000_cnt=32'h00fbc520 ;//0.5秒ごとの変化
// parameter F33M000_cnt=32'h00000010 ;//0.5秒ごとの変化
/**********************/
/*1秒カウンタ部 */
/**********************/
always @( posedge CLK )
if( reset == 1'b0)
sec_cnt <= 32'b0;
else begin
sec_cnt <= sec_cnt + 32'b1;
end
assign SCK = ~sec_cnt[2];
//基準クロック生成
always@(posedge SW2 or negedge reset)
begin
if(reset == 1'b0 )
begin
sw2_counter <= 1'b0 ;
sckmask <= 1'b0 ;
end
else if(sw2_counter == 1'b1)begin
sw2_counter <=1'b0 ;
sckmask <= 1'b0 ;
end else
begin
sw2_counter <= sw2_counter+ 1'b1 ;
sckmask <= 1'b1 ;
end
end
always@(posedge SW1 or negedge reset)//posedge SW1
begin
if(reset == 1'b0 )
reg_counter4 <= 4'b0000 ; //検証用に4'b****とする
else if(reg_counter4 == 4'b1010)
reg_counter4 <=4'b0000 ;
else
reg_counter4 <= reg_counter4 + 4'b0001 ;
end
assign counter4 = reg_counter4 ;//これがないと以降シミュレーションで表示されない。
always@(negedge SCK or negedge SW2 or negedge reset)
begin
if(reset == 1'b0)
begin
frame <= 1'b1 ;
reg_counter5 <= 5'b00000 ;
end
else if(SW2== 1'b0)
begin
frame <= 1'b1 ;
reg_counter5 <= 5'b00000 ;
end
else if(reg_counter5 == 5'b10000)begin
frame <= 1'b1 ;
reg_counter5 <= 5'b00000 ;
end
else
begin
reg_counter5 <= reg_counter5 + 5'b00001 ;
frame <= 1'b0 ;
end
end
assign sck_out = {~frame & SCK & sckmask} ;
assign counter5 = reg_counter5 ;
assign CS = frame ;
always@(negedge sck_out or negedge SW2 or negedge reset)
begin
if(reset == 1'b0)
begin
reg_countera5 <= 5'b00000 ;
end
else if(SW2== 1'b0)
begin
reg_countera5 <= 5'b00000 ;
end
else if(reg_countera5 == 5'b10000)begin
reg_countera5 <= 5'b00000 ;
end
else
begin
reg_countera5 <= reg_countera5 + 5'b00001 ;
end
end
assign countera5 = reg_countera5 ;
//
//7セグメント表示部
//
always@(negedge SW1 or negedge sck_out or negedge reset)
begin
case(counter4)
4'b0001 : reg_seg7 <= 8'b00111111 ; //'0'を表示 '1'が点灯()
4'b0010 : reg_seg7 <= 8'b00000110 ; //'1'を表示
4'b0011 : reg_seg7 <= 8'b01011011 ; //'2'を表示 --d0--
4'b0100 : reg_seg7 <= 8'b01001111 ; //'3'を表示 d5| |d1
4'b0101 : reg_seg7 <= 8'b01100110 ; //'4'を表示 --d6--
4'b0110 : reg_seg7 <= 8'b01101101 ; //'5'を表示 d4| |d2
4'b0111 : reg_seg7 <= 8'b01111101 ; //'6'を表示 --d3-- ○ d7
4'b1000 : reg_seg7 <= 8'b00100111 ; //'7'を表示
4'b1001 : reg_seg7 <= 8'b01111111 ; //'8'を表示
4'b1010 : reg_seg7 <= 8'b01101111 ; //'9'を表示
4'b1011 : reg_seg7 <= 8'b01110111 ; //'A'を表示
4'b1100 : reg_seg7 <= 8'b01111100 ; //'b'を表示
4'b1101 : reg_seg7 <= 8'b01011000 ; //'c'を表示
4'b1110 : reg_seg7 <= 8'b01011110 ; //'d'を表示
4'b1111 : reg_seg7 <= 8'b01111001 ; //'E'を表示
4'b0000 : reg_seg7 <= 8'b01110110 ; //'S'を表示 セット
default: ;
endcase
case(counter4)
4'b0000 : prl_n <= 16'b1000000000000000 ; //'0'[V]設定
4'b0001 : prl_n <= 16'b1000110011001100 ; //'1'[V]設定
4'b0010 : prl_n <= 16'b1001100110011001 ; //'2'[V]設定
4'b0011 : prl_n <= 16'b1010011001100110 ; //'3'[V]設定
4'b0100 : prl_n <= 16'b1011001100110011 ; //'4'[V]設定
4'b0101 : prl_n <= 16'b1100000000000000 ; //'5'[V]設定
4'b0110 : prl_n <= 16'b1100110011001100 ; //'6'[V]設定
4'b0111 : prl_n <= 16'b1101100110011001 ; //'7'[V]設定
4'b1000 : prl_n <= 16'b1110011001100110 ; //'8'[V]設定
4'b1001 : prl_n <= 16'b1111001100110011 ; //'9'[V]設定
4'b1010 : prl_n <= 16'b1111111111111111 ; //'A'10[V]設定
4'b1011 : prl_n <= 16'b1011001110001111 ; //'X'[V]設定
4'b1100 : prl_n <= 16'b1111111111111111 ; //'c'[V]設定
4'b1101 : prl_n <= 16'b1111111111111111 ; //'d'[V]設定
4'b1110 : prl_n <= 16'b1111111111111111 ; //'E'[V]設定
4'b1111 : prl_n <= 16'b1111111111111111 ; //'F'[V]設定
default: ;
endcase
if( reset == 1'b0 )
begin
sdata <= 16'b0000000000000000;
end
else
if( SW1 == 1'b0)
begin
sdata <= prl_n;
end
else
if( frame == 1'b1)
begin
sdata <= prl_n;
end
else
if(sck_out == 1'b0)
begin
sdata <= {sdata << 1};
end
end
assign PRL_N = prl_n ;
assign SDATA =sdata ;
assign SOUT = sdata[15] ;
assign seg7_n = ~reg_seg7 ;
endmodule
・1 TDAC_SPI †
`timescale 1ps/1ps
module testbench1;
reg CLK;
reg reset ;
reg SW1 ;
reg SW2 ;
wire[4:0] counter5 ;
wire[4:0] countera5 ;
wire[3:0] counter4 ;
wire[7:0] seg7_n ;
wire SCK ;
wire CS ;
wire sck_out ;
wire[15:0] SDATA ;
wire SOUT ;
wire [15:0] PRL_N ;
//clock generator//
// parameter F33M000_cnt = 32'h00000002;
parameter OSC33M_PERIOD = 3; // ns
// parameter SCK_PERIOD = 6; //ns
initial begin
CLK = 1'b0;
end
always #(OSC33M_PERIOD/2) begin
CLK <= ~CLK;
end
parameter STEP1 = 10;
parameter STEP2 = 1000;
parameter STEP3 = 50;
parameter STEP4 = 500;
DAC_SPI U1(
.CLK(CLK),
.reset(reset),
.SW1(SW1),
.SW2(SW2),
.counter4(counter4),
.counter5(counter5),
.countera5(countera5),
.seg7_n(seg7_n),
.CS(CS),
.SCK(SCK),
.sck_out(sck_out),
.SDATA(SDATA),
.SOUT(SOUT),
.PRL_N(PRL_N));
//initial CLK <= 0;
//always #(STEP1/4)
//CLK <= ~CLK;
initial reset <= 1;
initial SW1 <=1 ;
initial SW2 <=1 ;
initial SW2 <= 1;
initial begin
#2 reset <= 1'b1;
#2 SW1 <= 1'b1 ;
#2 reset <= 1'b0;
#22
#2 reset <= 1'b1;
#20
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //1
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //2
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //3
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //4
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //5
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //6
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //7
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //8
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //9
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //10
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //11
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //12
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //13
#20
#11 SW2 <= 1'b0;
#21 SW2 <= 1'b1;
#400
#2 reset <= 1'b0;
#20
#2 reset <= 1'b1;
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //1
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //2
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //2
#5
#21 SW2 <= 1'b0;
#21 SW2 <= 1'b1;
#400
#2 reset <= 1'b0;
#2 reset <= 1'b1;
end
endmodule
・1 DAC8871 table †
| 予備 | DEC | HEX | MSB | LSB | MSB | LSB | ＭＡＸ値 | VREFH | VREFL | 出力電圧[V] |
| 0 | 0000 | 00 | 00 | 00000000 | 00000000 | 65536 | 10 | -10 | -10.0000 |
| 1 | 0001 | 00 | 01 | 00000000 | 00000001 | 65536 | 10 | -10 | -9.9997 |
| 3 | 0003 | 00 | 03 | 00000000 | 00000011 | 65536 | 10 | -10 | -9.9991 |
| 7 | 0007 | 00 | 07 | 00000000 | 00000111 | 65536 | 10 | -10 | -9.9979 |
| 15 | 000F | 00 | 0F | 00000000 | 00001111 | 65536 | 10 | -10 | -9.9954 |
| 31 | 001F | 00 | 1F | 00000000 | 00011111 | 65536 | 10 | -10 | -9.9905 |
| 63 | 003F | 00 | 3F | 00000000 | 00111111 | 65536 | 10 | -10 | -9.9808 |
| 127 | 007F | 00 | 7F | 00000000 | 01111111 | 65536 | 10 | -10 | -9.9612 |
| 255 | 00FF | 00 | FF | 00000000 | 11111111 | 65536 | 10 | -10 | -9.9222 |
| 511 | 01FF | 01 | FF | 00000001 | 11111111 | 65536 | 10 | -10 | -9.8441 |
| 1023 | 03FF | 03 | FF | 00000011 | 11111111 | 65536 | 10 | -10 | -9.6878 |
| 2047 | 07FF | 07 | FF | 00000111 | 11111111 | 65536 | 10 | -10 | -9.3753 |
| 4095 | 0FFF | 0F | FF | 00001111 | 11111111 | 65536 | 10 | -10 | -8.7503 |
| 8191 | 1FFF | 1F | FF | 00011111 | 11111111 | 65536 | 10 | -10 | -7.5003 |
| 16383 | 3FFF | 3F | FF | 00111111 | 11111111 | 65536 | 10 | -10 | -5.0003 |
| 24575 | 5FFF | 5F | FF | 01011111 | 11111111 | 65536 | 10 | -10 | -2.5003 |
| 32767 | 7FFF | 7F | FF | 01111111 | 11111111 | 65536 | 10 | -10 | -0.0003 |
| 1 | 32768 | 8000 | 80 | 00 | 10000000 | 00000000 | 65536 | 10 | -10 | 0.0000 |
| 2 | 32769 | 8001 | 80 | 01 | 10000000 | 00000001 | 65536 | 10 | -10 | 0.0003 |
| 4 | 32771 | 8003 | 80 | 03 | 10000000 | 00000011 | 65536 | 10 | -10 | 0.0009 |
| 8 | 32775 | 8007 | 80 | 07 | 10000000 | 00000111 | 65536 | 10 | -10 | 0.0021 |
| 16 | 32783 | 800F | 80 | 0F | 10000000 | 00001111 | 65536 | 10 | -10 | 0.0046 |
| 32 | 32799 | 801F | 80 | 1F | 10000000 | 00011111 | 65536 | 10 | -10 | 0.0095 |
| 64 | 32831 | 803F | 80 | 3F | 10000000 | 00111111 | 65536 | 10 | -10 | 0.0192 |
| 128 | 32895 | 807F | 80 | 7F | 10000000 | 01111111 | 65536 | 10 | -10 | 0.0388 |
| 256 | 33023 | 80FF | 80 | FF | 10000000 | 11111111 | 65536 | 10 | -10 | 0.0778 |
| 512 | 33279 | 81FF | 81 | FF | 10000001 | 11111111 | 65536 | 10 | -10 | 0.1559 |
| 1024 | 33791 | 83FF | 83 | FF | 10000011 | 11111111 | 65536 | 10 | -10 | 0.3122 |
| 2048 | 34815 | 87FF | 87 | FF | 10000111 | 11111111 | 65536 | 10 | -10 | 0.6247 |
| 4096 | 36863 | 8FFF | 8F | FF | 10001111 | 11111111 | 65536 | 10 | -10 | 1.2497 |
| 8192 | 40959 | 9FFF | 9F | FF | 10011111 | 11111111 | 65536 | 10 | -10 | 2.4997 |
| 16384 | 49151 | BFFF | BF | FF | 10111111 | 11111111 | 65536 | 10 | -10 | 4.9997 |
| 32768 | 65535 | FFFF | FF | FF | 11111111 | 11111111 | 65536 | 10 | -10 | 9.9997 |
・1 DAC_SPI2 †
module DAC_SPI_3(
CLK,
reset ,
SW1,
SW2,
CS,
seg7_n,
SW2_COUNTER,
counter4,
counter5,
countera5,
SCK,
sck_out,
SDATA,
SOUT,
PRL_N
);
//******蜈･蜃ｺ蜉・*****//a
input CLK;
input reset ;
input SW1 ;
input SW2 ;
output CS ;
output[7:0] seg7_n ;
output[3:0] counter4 ;
output[4:0] counter5 ;
output[5:0] countera5 ;
output SW2_COUNTER ;
output SCK ;
output sck_out ;
output[15:0] SDATA ;
output SOUT;
output[15:0] PRL_N ;
//******蜀・Κ繝弱・繝・*****//
reg [31:0] sec_cnt ;//・醍ｧ剃ｽ懈・逕ｨ繧ｫ繧ｦ繝ｳ繧ｿ
reg[3:0] reg_counter4 ; //繝懊ち繝ｳ蜈･蜉帛屓謨ｰ
reg[4:0] reg_counter5 ;//16bit 1繝輔Ξ繝ｼ繝菴懈・
reg[4:0] reg_countera5 ;
reg sw1 ;
reg sw2 ;
reg sw2_counter ;
reg frame ;//16bit 1繝輔Ξ繝ｼ繝繝輔Λ繧ｰ
reg sck ;//sck縺ｮcs縲€low縺ｮ縺ｨ縺阪・繝槭せ繧ｯ
reg[7:0] reg_seg7 ;//7seg縺ｸ縺ｮ蜃ｺ蜉帙ヰ繝・ヵ繧｡
reg[15:0] prl_n ;
reg[15:0] sdata ;
reg sckmask ;
//******蜀・Κ蝗櫁ｷｯ******//
initial frame <= 1'b1 ;
//initial reg_counter5 <= 5'b00000 ;
//initial prl_n= 16'hF0F0 ;
//
//繧ｫ繧ｦ繝ｳ繧ｿ驛ｨ
//蝓ｺ貅悶け繝ｭ繝・け繧ｫ繧ｦ繝ｳ繧ｿ//
//parameter F33M000_cnt=32'h00fbc520 ;//0.5遘偵＃縺ｨ縺ｮ螟牙喧
// parameter F33M000_cnt=32'h00000010 ;//0.5遘偵＃縺ｨ縺ｮ螟牙喧
/**********************/
/*1遘偵き繧ｦ繝ｳ繧ｿ驛ｨ */
/**********************/
always@( posedge CLK )
begin
if( reset == 1'b0)
begin
sec_cnt <= 32'b0;
end else
begin
sec_cnt <= sec_cnt + 32'b1;
sck <= ~sec_cnt[2];
end
end
always@(negedge CLK)
begin
sw1 <= SW1 ;
end
assign SCK = sck ;
assign sck_out = {sck & sw2_counter } ;
always@(posedge SW2 or negedge reset)
begin
if(reset == 1'b0)
begin
sw2_counter <=1'b0 ;
sw2 <= 1'b1 ;
end
else if(sw2_counter == 1'b1)
begin
sw2_counter <= 1'b1 ;
sw2 <= 1'b1 ;
end
else
begin
sw2_counter <= sw2_counter + 1'b1 ;
sw2 <= 1'b0 ;
end
end
assign SW2_COUNTER = sw2_counter ;
always@(negedge sck_out or negedge reset)
begin
if(reset == 1'b0)
begin
reg_counter5 <= 5'b00000 ;
frame <= 1'b1 ;
end
else if(reg_counter5 == 5'b10000)
begin
reg_counter5 <= 5'b00000 ;
frame <= 1'b1 ;
end
else
begin
reg_counter5 <= reg_counter5 + 1'b1 ;
frame <= reg_counter5[4] ;
end
end
assign counter5 = reg_counter5 ;
always@(negedge SW1 or negedge reset)//posedge SW1
begin
if(reset == 1'b0 )
reg_counter4 <= 4'b0000 ; //讀懆ｨｼ逕ｨ縺ｫ4'b****縺ｨ縺吶ｋ
else if(reg_counter4 == 4'b1010)
reg_counter4 <=4'b0000 ;
else
reg_counter4 <= reg_counter4 + 4'b0001 ;
end
assign counter4 = reg_counter4 ;//縺薙ｌ縺後↑縺・→莉･髯阪す繝溘Η繝ｬ繝ｼ繧ｷ繝ｧ繝ｳ縺ｧ陦ｨ遉ｺ縺輔ｌ縺ｪ縺・€・
assign CS = frame ;
always@(negedge sw1 or negedge sck_out or negedge reset or negedge CLK)// negedge sck_out
begin
case(reg_counter4)
4'b0001 : reg_seg7 <= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ縲€'1'縺檎せ轣ｯ()
4'b0010 : reg_seg7 <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0011 : reg_seg7 <= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ 縲€--d0--
4'b0100 : reg_seg7 <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ d5| |d1
4'b0101 : reg_seg7 <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ --d6--
4'b0110 : reg_seg7 <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ d4| |d2
4'b0111 : reg_seg7 <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ --d3-- 笳・d7
4'b1000 : reg_seg7 <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ縲€縲€
4'b1001 : reg_seg7 <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1010 : reg_seg7 <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1011 : reg_seg7 <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1100 : reg_seg7 <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1101 : reg_seg7 <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1110 : reg_seg7 <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1111 : reg_seg7 <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b0000 : reg_seg7 <= 8'b01110110 ; //'S'繧定｡ｨ遉ｺ 繧ｻ繝・ヨ
default : reg_seg7 <= 8'b00111111 ;
endcase
case(reg_counter4)
4'b0000 : prl_n <= 16'b1000000000000000 ; //'0'[V]險ｭ螳・
4'b0001 : prl_n <= 16'b1000110011001100 ; //'1'[V]險ｭ螳・
4'b0010 : prl_n <= 16'b1001100110011001 ; //'2'[V]險ｭ螳・
4'b0011 : prl_n <= 16'b1010011001100110 ; //'3'[V]險ｭ螳・
4'b0100 : prl_n <= 16'b1011001100110011 ; //'4'[V]險ｭ螳・
4'b0101 : prl_n <= 16'b1100000000000000 ; //'5'[V]險ｭ螳・
4'b0110 : prl_n <= 16'b1100110011001100 ; //'6'[V]險ｭ螳・
4'b0111 : prl_n <= 16'b1101100110011001 ; //'7'[V]險ｭ螳・
4'b1000 : prl_n <= 16'b1110011001100110 ; //'8'[V]險ｭ螳・
4'b1001 : prl_n <= 16'b1111001100110011 ; //'9'[V]險ｭ螳・
4'b1010 : prl_n <= 16'b1111111111111111 ; //'A'10[V]險ｭ螳・
4'b1011 : prl_n <= 16'b1011001110001111 ; //'X'[V]險ｭ螳・
4'b1100 : prl_n <= 16'b1111111111111111 ; //'c'[V]險ｭ螳・
4'b1101 : prl_n <= 16'b1111111111111111 ; //'d'[V]險ｭ螳・
4'b1110 : prl_n <= 16'b1111111111111111 ; //'E'[V]險ｭ螳・
4'b1111 : prl_n <= 16'b1111111111111111 ; //'F'[V]險ｭ螳・
default: prl_n <= 16'b1000000000000000 ;
endcase
if( reset == 1'b0 )
begin
sdata <= 16'b1000000000000000;
prl_n <= 16'b1000000000000000;
end
else if(CLK == 1'b0)
begin
sdata <= prl_n ;
end
else
if(sck_out ==1'b0)
begin
sdata <= {sdata << 1};
end
end
// if( reset == 1'b0 )
// begin
// sdata <= 16'b0000000000000000;
// end
// else
// if( SW1 == 1'b0)
// begin
// sdata <= prl_n;
// end
// else
// if( frame == 1'b1)
// begin
// sdata <= prl_n;
// end
// else
// if(sck_out == 1'b0)
// begin
// sdata <= {sdata << 1};
// end
//end
assign PRL_N = prl_n ;
assign SDATA =sdata ;
assign SOUT = sdata[15] ;
assign seg7_n = ~reg_seg7 ;
endmodule
・1 TAC_SPI2 †
`timescale 1ps/1ps
module testbench1;
reg CLK;
reg reset ;
reg SW1 ;
reg SW2 ;
wire SW2_COUNTER ;
wire[4:0] counter5 ;
wire[4:0] countera5 ;
wire[3:0] counter4 ;
wire[7:0] seg7_n ;
wire SCK ;
wire CS ;
wire sck_out ;
wire[15:0] SDATA ;
wire SOUT ;
wire [15:0] PRL_N ;
//clock generator//
// parameter F33M000_cnt = 32'h00000002;
parameter OSC33M_PERIOD = 3; // ns
// parameter SCK_PERIOD = 6; //ns
initial begin
CLK = 1'b0;
end
always #(OSC33M_PERIOD/2) begin
CLK <= ~CLK;
end
parameter STEP1 = 10;
parameter STEP2 = 1000;
parameter STEP3 = 50;
parameter STEP4 = 500;
DAC_SPI_3 U1(
.CLK(CLK),
.reset(reset),
.SW1(SW1),
.SW2(SW2),
.counter4(counter4),
.counter5(counter5),
.countera5(countera5),
.seg7_n(seg7_n),
.CS(CS),
.SCK(SCK),
.sck_out(sck_out),
.SDATA(SDATA),
.SOUT(SOUT),
.SW2_COUNTER(SW2_COUNTER) ,
.PRL_N(PRL_N));
//initial CLK <= 0;
//always #(STEP1/4)
//CLK <= ~CLK;
initial reset <= 1;
initial SW1 <=1 ;
initial SW2 <=1 ;
initial SW2 <= 1;
initial begin
#2 reset <= 1'b1;
#2 SW1 <= 1'b1 ;
#2 reset <= 1'b0;
#22
#2 reset <= 1'b1;
#20
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //1
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //2
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //3
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //4
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //5
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //6
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //7
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //8
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //9
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //10
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //11
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //12
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //13
#20
#11 SW2 <= 1'b0;
#21 SW2 <= 1'b1;
#400
#2 reset <= 1'b0;
#20
#2 reset <= 1'b1;
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //1
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //2
#5 SW1 <= 1'b0;
#2 SW1 <= 1'b1; //2
#5
#21 SW2 <= 1'b0;
#21 SW2 <= 1'b1;
#400
#2 reset <= 1'b0;
#2 reset <= 1'b1;
end
endmodule
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