verilog
・1 7segダイナミック点灯 †
module seg7_dynamic(
SW1,
SW2,
SW3,
SW4,
CLK,
SCK,
RST,
SEVEN_SEG_DATA[7:0],
SEL[4:1]
);
// in out definiton//
input CLK;
input RST;
input SW1;
input SW2;
input SW3;
input SW4;
output SCK;
output reg[7:0] SEVEN_SEG_DATA;
output [4:1] SEL;
//internal resister//
reg sw1;
reg sw2;
reg sw3;
reg sw4;
reg[16:0] sw1_counter;
reg[16:0] sw2_counter;
reg[16:0] sw3_counter;
reg[16:0] sw4_counter;
reg[31:0] sec_cnt; //slow clock generation
reg sec1_flag; //slow clock generation
reg toggle_flag; //slow clock generation
reg[1:0] enable_seg;
reg[4:1] sel;
reg[3:0] seven_seg1_counter;
reg[3:0] seven_seg2_counter;
reg[3:0] seven_seg3_counter;
reg[3:0] seven_seg4_counter;
reg[7:0] seven_seg1_hold;
reg[7:0] seven_seg2_hold;
reg[7:0] seven_seg3_hold;
reg[7:0] seven_seg4_hold;
reg[7:0] seven_seg;
reg sck;
//parameter F33M000_cnt=32'h004c4b40 ;//0.5sec interval
//parameter F33M000_cnt=32'h000f4240 ;//0.5sec interval
//parameter F33M000_cnt=32'h0000c350 ;//0.05sec interval
parameter F33M000_cnt=32'h00002721 ;//0.001sec interval
//parameter F33M000_cnt=32'h000186A0 ;//0.1sec interval
parameter selinit_value = 4'b1000 ;
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw1_counter <= 16'b0000000000000000;
end else begin
sw1_counter <= sw1_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw1_counter ==0)begin
sw1 <= SW1;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw2_counter <= 16'b0000000000000000;
end else begin
sw2_counter <= sw2_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw2_counter ==0)begin
sw2 <= SW2;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw3_counter <= 16'b0000000000000000;
end else begin
sw3_counter <= sw3_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw3_counter ==0)begin
sw3 <= SW3;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw4_counter <= 16'b0000000000000000;
end else begin
sw4_counter <= sw4_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw4_counter ==0)begin
sw4 <= SW4;
end
end
always@(posedge CLK)
begin
if(sec_cnt == F33M000_cnt) begin
sec_cnt <= 32'h00000000 ; //counter counting up
sec1_flag <= 1'b1;
end else begin
sec_cnt <= sec_cnt + 1 ;
sec1_flag <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag == 1'b1 )begin
toggle_flag <= !toggle_flag ;
end
end
assign SCK = !toggle_flag;
always@(negedge sw1 or negedge sw2 or negedge sw3 or negedge sw4 or negedge RST or posedge CLK)
begin if(RST ==1'b0)begin
seven_seg1_hold <=8'b00000110;
seven_seg2_hold <=8'b00000110;
seven_seg3_hold <=8'b00000110;
seven_seg4_hold <=8'b00000110;
end else begin
case(seven_seg1_counter)
4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg1_hold <= 8'b00000110;
endcase
case(seven_seg2_counter)
4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg2_hold <= 8'b00000110;
endcase
case(seven_seg3_counter)
4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg3_hold <= 8'b00000110;
endcase
case(seven_seg4_counter)
4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg4_hold <= 8'b00000110;
endcase
end
end
always@(posedge SCK or negedge RST)begin
if(RST == 1'b0 )begin
enable_seg <= 2'b00;
end else begin
enable_seg <= enable_seg +1'b1;
end
end
//always@(negedge RST)begin
// if(RST == 1'b0 )begin
// seven_seg <= 7'b0;
// end else if(SEL[1] == 1'b1)begin
// seven_seg[7:1] <=seven_seg1_hold[7:1];
// end else if(SEL[2] == 1'b1)begin
// seven_seg[7:1] <=seven_seg2_hold[7:1];
// end else if(SEL[3]== 1'b1)begin
// seven_seg[7:1] <=seven_seg3_hold[7:1];
// end else if(SEL[4] ==1'b1)begin
// seven_seg[7:1] <=seven_seg4_hold[7:1];
// end
//end
//assign SEVEN_SEG_DATA[7:0] =(enable_seg == 2'b01) ? seven_seg1_hold[7:0] :(enable_seg == 2'b10) ? seven_seg2_hold[7:0]:(enable_seg
== 2'b11) ? seven_seg3_hold[7:0]:(enable_seg == 2'b00) ? seven_seg4_hold[7:0]:8'b0;
// assign SEVEN_SEG_DATA[7:0] = seven_seg[7:0];
always@(posedge SCK or negedge RST)begin
if(RST == 1'b0 )begin
sel <= selinit_value;
end else begin
sel[2] <= sel[1] ; //シフト動作を開始する
sel[3] <= sel[2] ; //シフト動作を開始する
sel[4] <= sel[3] ; //シフト動作を開始する
sel[1] <= sel[4] ;
end
end
assign SEL[4:1] = ~sel[4:1];
always@( negedge RST or posedge sw1 )begin
if( RST == 1'b0 )begin
seven_seg1_counter <= 4'b0000;
end else begin
seven_seg1_counter <= seven_seg1_counter + 1'b1;
end
end
always@( negedge RST or negedge sw2)begin
if( RST == 1'b0)begin
seven_seg2_counter <= 4'b0000;
end else begin
seven_seg2_counter <= seven_seg2_counter + 1'b1;
end
end
always@( negedge RST or negedge sw3)begin
if( RST == 1'b0)begin
seven_seg3_counter <= 4'b0000;
end else begin
seven_seg3_counter <= seven_seg3_counter + 1'b1;
end
end
always@( negedge RST or negedge sw4)begin
if( RST == 1'b0)begin
seven_seg4_counter <= 4'b0000;
end else begin
seven_seg4_counter <= seven_seg4_counter + 1'b1;
end
end
always@*
begin
case(enable_seg)
// 2'b00: seven_seg<=~seven_seg4_hold;
2'b00: SEVEN_SEG_DATA <= ~seven_seg4_hold;
2'b01: SEVEN_SEG_DATA<=~seven_seg1_hold;
2'b10: SEVEN_SEG_DATA<=~seven_seg2_hold;
2'b11: SEVEN_SEG_DATA<=~seven_seg3_hold;
// default: SEVEN_SEG1_DATA <= 8'b00000000;
endcase
end
endmodule
・1 7segダイナミック点灯2 †
module seg7_dynamic2(
SW1, //input LSB
SW2,
SW3,
SW4, //input MSB
SW5,//set out
CLK,
SCK,
NSCK,
RST,
SEVEN_SEG_DATA[7:0],
SEL[4:1],
SOUT
);
// in out definiton//
input CLK;
input RST;
input SW1;
input SW2;
input SW3;
input SW4;
input SW5;
output SCK;
output NSCK;
output reg[7:0] SEVEN_SEG_DATA;
output [4:1] SEL;
output SOUT;
//internal resister//
reg[32:0]SPI_WORD_DATA;
reg sw1;
reg sw2;
reg sw3;
reg sw4;
reg sw5;
//reg sw5in;
reg sw5out;
reg sout;
reg[16:0] sw1_counter;
reg[16:0] sw2_counter;
reg[16:0] sw3_counter;
reg[16:0] sw4_counter;
reg[16:0] sw5_counter;
reg[31:0] sec_cnt; //slow clock generation
reg sec1_flag; //slow clock generation
reg toggle_flag; //slow clock generation
reg[1:0] enable_seg;
reg[4:1] sel;
reg[3:0] seven_seg1_counter;
reg[3:0] seven_seg2_counter;
reg[3:0] seven_seg3_counter;
reg[3:0] seven_seg4_counter;
reg[7:0] seven_seg1_hold;
reg[7:0] seven_seg2_hold;
reg[7:0] seven_seg3_hold;
reg[7:0] seven_seg4_hold;
reg[7:0] seven_seg;
reg sck;
reg ncs;
reg nsck;
reg[4:1]cs_counter;
reg[7:0] seven_word_data;
initial ncs <= 1'b1 ;
//parameter F33M000_cnt=32'h004c4b40 ;//0.5sec interval
//parameter F33M000_cnt=32'h000f4240 ;//0.5sec interval
//parameter F33M000_cnt=32'h0000c350 ;//0.05sec interval
parameter F33M000_cnt=32'h00002721 ;//0.001sec interval inputting clk: at 10Mhz
//parameter F33M000_cnt=32'h000186A0 ;//0.1sec interval
parameter selinit_value = 4'b1000 ;
//***chattring rejection***//
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw1_counter <= 16'b0000000000000000; //16bit 65535times(aprroximately 6.5msec sampling)
end else begin
sw1_counter <= sw1_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw1_counter ==0)begin
sw1 <= SW1;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw2_counter <= 16'b0000000000000000;
end else begin
sw2_counter <= sw2_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw2_counter ==0)begin
sw2 <= SW2;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw3_counter <= 16'b0000000000000000;
end else begin
sw3_counter <= sw3_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw3_counter ==0)begin
sw3 <= SW3;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw4_counter <= 16'b0000000000000000;
end else begin
sw4_counter <= sw4_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw4_counter ==0)begin
sw4 <= SW4;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw5_counter <= 16'b0000000000000000;
end else begin
sw5_counter <= sw5_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw5_counter ==0)begin
sw5 <= SW5;
end
end
//***The end of chattring rejection***//
always@(posedge CLK)
begin
if(sec_cnt == F33M000_cnt) begin
sec_cnt <= 32'h00000000 ; //counter counting up to the parameter(refer to No 52th row)
sec1_flag <= 1'b1;
end else begin
sec_cnt <= sec_cnt + 1 ;
sec1_flag <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag == 1'b1 )begin
toggle_flag <= !toggle_flag ;
end
end
assign SCK = !toggle_flag;
assign NSCK =toggle_flag;
always@(negedge sw1 or negedge sw2 or negedge sw3 or negedge sw4 or negedge RST or posedge CLK)
begin if(RST ==1'b0)begin
seven_seg1_hold <=8'b00000110;
seven_seg2_hold <=8'b00000110;
seven_seg3_hold <=8'b00000110;
seven_seg4_hold <=8'b00000110;
end else begin
case(seven_seg1_counter)
4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0'
4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1'
4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2'
4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3'
4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4'
4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5'
4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6'
4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7'
4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8'
4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9'
4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A'
4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b'
4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c'
4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d'
4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E'
4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F'
default: seven_seg1_hold <= 8'b00000110;
endcase
case(seven_seg2_counter)
4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg2_hold <= 8'b00000110;
endcase
case(seven_seg3_counter)
4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg3_hold <= 8'b00000110;
endcase
case(seven_seg4_counter)
4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0'繧定｡ｨ遉ｺ
4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1'繧定｡ｨ遉ｺ
4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2'繧定｡ｨ遉ｺ
4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3'繧定｡ｨ遉ｺ
4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4'繧定｡ｨ遉ｺ
4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5'繧定｡ｨ遉ｺ
4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6'繧定｡ｨ遉ｺ
4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7'繧定｡ｨ遉ｺ
4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8'繧定｡ｨ遉ｺ
4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9'繧定｡ｨ遉ｺ
4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A'繧定｡ｨ遉ｺ
4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b'繧定｡ｨ遉ｺ
4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c'繧定｡ｨ遉ｺ
4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d'繧定｡ｨ遉ｺ
4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E'繧定｡ｨ遉ｺ
4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F'繧定｡ｨ遉ｺ
default: seven_seg4_hold <= 8'b00000110;
endcase
end
end
always@(posedge SCK or negedge RST)begin
if(RST == 1'b0 )begin
enable_seg <= 2'b00;
end else begin
enable_seg <= enable_seg +1'b1;
end
end
always@(posedge SCK or negedge RST)begin
if(RST == 1'b0 )begin
sel <= selinit_value;
end else begin
sel[2] <= sel[1] ; //シフト動作を開始する
sel[3] <= sel[2] ; //シフト動作を開始する
sel[4] <= sel[3] ; //シフト動作を開始する
sel[1] <= sel[4] ;
end
end
assign SEL[4:1] = ~sel[4:1];
always@( negedge RST or posedge sw1 )begin
if( RST == 1'b0 )begin
seven_seg1_counter <= 4'b0000;
end else begin
seven_seg1_counter <= seven_seg1_counter + 1'b1;
end
end
always@( negedge RST or negedge sw2)begin
if( RST == 1'b0)begin
seven_seg2_counter <= 4'b0000;
end else begin
seven_seg2_counter <= seven_seg2_counter + 1'b1;
end
end
always@( negedge RST or negedge sw3)begin
if( RST == 1'b0)begin
seven_seg3_counter <= 4'b0000;
end else begin
seven_seg3_counter <= seven_seg3_counter + 1'b1;
end
end
always@( negedge RST or negedge sw4)begin
if( RST == 1'b0)begin
seven_seg4_counter <= 4'b0000;
end else begin
seven_seg4_counter <= seven_seg4_counter + 1'b1;
end
end
always@*
begin
case(enable_seg)
// 2'b00: seven_seg<=~seven_seg4_hold;
2'b00: SEVEN_SEG_DATA <= ~seven_seg4_hold;
2'b01: SEVEN_SEG_DATA<=~seven_seg1_hold;
2'b10: SEVEN_SEG_DATA<=~seven_seg2_hold;
2'b11: SEVEN_SEG_DATA<=~seven_seg3_hold;
// default: SEVEN_SEG1_DATA <= 8'b00000000;
endcase
end
always@(posedge CLK or negedge RST)
if(RST == 1'b0)begin
seven_word_data <=16'b0000000000000000;
begin
seven_word_data <= {seven_seg4_hold,seven_seg3_hold,seven_seg2_hold,seven_seg1_hold};
end
end
always@( negedge RST or negedge sw5 )begin
if( RST == 1'b0)begin
sw5out <= 1'b1;
end else if(sw5 == 1'b0)begin
sw5out <= 1'b1;
end
end
always@(posedge SCK or negedge RST)
begin
if(RST == 1'b0 )begin
cs_counter<= 4'b1111;
ncs <=1;
end else if(cs_counter < 4'b1111 )begin
cs_counter <= cs_counter +1'b1;
ncs <=0;
end else begin
ncs <=1;
end
end
always@(posedge SCK or negedge RST or negedge ncs )begin
if(RST == 1'b0 )begin
sout<= 1'b0;
end else if(ncs == 1'b0 )
begin
sout<=seven_word_data;
sout <= {sout<<1 };
end
end
assign SOUT = sout & !sw5out ;
endmodule
・1 7segダイナミック点灯2 †
module seg7_dynamic2(
SW1, //input LSB
SW2,
SW3,
SW4, //input MSB
SW5,//set out
CLK,
SCK,
NSCK,
NCS,
RST,
SEVEN_SEG_DATA[7:0],
SEL[4:1],
SOUT
);
// in out definiton//
input CLK;
input RST;
input SW1;
input SW2;
input SW3;
input SW4;
input SW5;
output SCK;
output NSCK;
output NCS;
output reg[7:0] SEVEN_SEG_DATA;
output [4:1] SEL;
output SOUT;
//internal resister//
reg[31:0]SPI_WORD_DATA;
reg sw1;
reg sw2;
reg sw3;
reg sw4;
reg sw5;
//reg sw5in;
reg sw5out;
reg [31:0] sout;
reg[16:0] sw1_counter;
reg[16:0] sw2_counter;
reg[16:0] sw3_counter;
reg[16:0] sw4_counter;
reg[16:0] sw5_counter;
reg[31:0] sec_cnt; //slow clock generation
reg sec1_flag; //slow clock generation
reg toggle_flag; //slow clock generation
reg[1:0] enable_seg;
reg[4:1] sel;
reg[3:0] seven_seg1_counter;
reg[3:0] seven_seg2_counter;
reg[3:0] seven_seg3_counter;
reg[3:0] seven_seg4_counter;
reg[7:0] seven_seg1_hold;
reg[7:0] seven_seg2_hold;
reg[7:0] seven_seg3_hold;
reg[7:0] seven_seg4_hold;
reg[7:0] seven_seg;
reg sck;
reg ncs;
reg nsck;
reg[4:1]cs_counter;
reg[7:0] seven_word_data;
initial ncs <= 1'b1 ;
//parameter F33M000_cnt=32'h004c4b40 ;//0.5sec interval
//parameter F33M000_cnt=32'h000f4240 ;//0.5sec interval
//parameter F33M000_cnt=32'h0000c350 ;//0.05sec interval
parameter F33M000_cnt=32'h00002721 ;//0.001sec interval inputting clk: at 10Mhz
//parameter F33M000_cnt=32'h000186A0 ;//0.1sec interval
parameter selinit_value = 4'b1000 ;
//***chattring rejection***//
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw1_counter <= 16'b0000000000000000; //16bit 65535times(aprroximately 6.5msec sampling)
end else begin
sw1_counter <= sw1_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw1_counter ==0)begin
sw1 <= SW1;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw2_counter <= 16'b0000000000000000;
end else begin
sw2_counter <= sw2_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw2_counter ==0)begin
sw2 <= SW2;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw3_counter <= 16'b0000000000000000;
end else begin
sw3_counter <= sw3_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw3_counter ==0)begin
sw3 <= SW3;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw4_counter <= 16'b0000000000000000;
end else begin
sw4_counter <= sw4_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw4_counter ==0)begin
sw4 <= SW4;
end
end
always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw5_counter <= 16'b0000000000000000;
end else begin
sw5_counter <= sw5_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw5_counter ==0)begin
sw5 <= SW5;
end
end
//***The end of chattring rejection***//
always@(posedge CLK)
begin
if(sec_cnt == F33M000_cnt) begin
sec_cnt <= 32'h00000000 ; //counter counting up to the parameter(refer to No 52th row)
sec1_flag <= 1'b1;
end else begin
sec_cnt <= sec_cnt + 1 ;
sec1_flag <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag == 1'b1 )begin
toggle_flag <= !toggle_flag ;
end
end
assign SCK = !toggle_flag;
assign NSCK =toggle_flag;
always@(negedge sw1 or negedge sw2 or negedge sw3 or negedge sw4 or negedge RST or posedge CLK)
begin if(RST ==1'b0)begin
seven_seg1_hold <=8'b00000110;
seven_seg2_hold <=8'b00000110;
seven_seg3_hold <=8'b00000110;
seven_seg4_hold <=8'b00000110;
end else begin
case(seven_seg1_counter)
4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0'
4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1'
4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2'
4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3'
4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4'
4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5'
4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6'
4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7'
4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8'
4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9'
4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A'
4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b'
4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c'
4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d'
4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E'
4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F'
default: seven_seg1_hold <= 8'b00000110;
endcase
case(seven_seg2_counter)
4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
default: seven_seg2_hold <= 8'b00000110;
endcase
case(seven_seg3_counter)
4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
default: seven_seg3_hold <= 8'b00000110;
endcase
case(seven_seg4_counter)
4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F'郢ｧ螳夲ｽ｡・ｨ驕会ｽｺ
default: seven_seg4_hold <= 8'b00000110;
endcase
end
end
always@(posedge SCK or negedge RST)begin
if(RST == 1'b0 )begin
enable_seg <= 2'b00;
end else begin
enable_seg <= enable_seg +1'b1;
end
end
always@(posedge SCK or negedge RST)begin
if(RST == 1'b0 )begin
sel <= selinit_value;
end else begin
sel[2] <= sel[1] ; //繧ｷ繝輔ヨ蜍穂ｽ懊ｒ髢句ｧ九☆繧・
sel[3] <= sel[2] ; //繧ｷ繝輔ヨ蜍穂ｽ懊ｒ髢句ｧ九☆繧・
sel[4] <= sel[3] ; //繧ｷ繝輔ヨ蜍穂ｽ懊ｒ髢句ｧ九☆繧・
sel[1] <= sel[4] ;
end
end
assign SEL[4:1] = ~sel[4:1];
always@( negedge RST or posedge sw1 )begin
if( RST == 1'b0 )begin
seven_seg1_counter <= 4'b0000;
end else begin
seven_seg1_counter <= seven_seg1_counter + 1'b1;
end
end
always@( negedge RST or negedge sw2)begin
if( RST == 1'b0)begin
seven_seg2_counter <= 4'b0000;
end else begin
seven_seg2_counter <= seven_seg2_counter + 1'b1;
end
end
always@( negedge RST or negedge sw3)begin
if( RST == 1'b0)begin
seven_seg3_counter <= 4'b0000;
end else begin
seven_seg3_counter <= seven_seg3_counter + 1'b1;
end
end
always@( negedge RST or negedge sw4)begin
if( RST == 1'b0)begin
seven_seg4_counter <= 4'b0000;
end else begin
seven_seg4_counter <= seven_seg4_counter + 1'b1;
end
end
always@*
begin
case(enable_seg)
// 2'b00: seven_seg<=~seven_seg4_hold;
2'b00: SEVEN_SEG_DATA <= ~seven_seg4_hold;
2'b01: SEVEN_SEG_DATA<=~seven_seg1_hold;
2'b10: SEVEN_SEG_DATA<=~seven_seg2_hold;
2'b11: SEVEN_SEG_DATA<=~seven_seg3_hold;
// default: SEVEN_SEG1_DATA <= 8'b00000000;
endcase
end
always@( negedge RST or negedge sw5 )begin
if( RST == 1'b0)begin
sw5out <= 1'b1;
end else if(sw5 == 1'b0)begin
sw5out <= 1'b0;
end else begin
sw5out <=1'b0;
end
end
always@(posedge SCK or negedge RST or negedge sw5out)
begin
if(RST == 1'b0 )begin
cs_counter<= 4'b0000;
end else if(sw5out == 1'b0)begin
cs_counter <= cs_counter +1'b1;
end else begin
cs_counter <=4'b0101;
end
end
assign NCS = !cs_counter[4];
always@(posedge SCK or negedge RST or negedge NCS )begin
if(RST == 1'b0 )begin
sout<=32'b11111111111111111111111111111111;
end else if(NCS == 1'b0)
begin
sout <= {seven_seg4_hold,seven_seg3_hold,seven_seg2_hold,seven_seg1_hold};
end else begin
sout <= {sout<<1 };
end
end
//assign SOUT = sout[31] & !sw5out ;
assign SOUT = sout[31] ;
endmodule
・LPC_PORT80h_decoder4 †
module LPC_PORT80h_decoder4(
CLK, //standard clock
RST,
LADCOM[3:0],
//PNFRAME,
SW1,
//STAT[3:0],
//AD[15:0],
//ONFRAME,
//SEVEN_SEG_DATA[7:0],
NRCOUNTER[16:0],
NFRAME,
COMOUT[3:0],
SCK,
NSCK,
SCK2,
WRCYC,
SEVEN_SEG_DATA[7:0],
SEL[4:1],
DSEL[2:1],
DSEVEN_SEG_DATA[7:0],
CS_COUNTER[4:0]
);
// in/out definiton//
input CLK;
input RST;
input[3:0] LADCOM;
// input PNFRAME;
input SW1;
// output reg[7:0] SEVEN_SEG_DATA;
output[16:0] NRCOUNTER;
output NFRAME;
output SCK;
output NSCK;
output SCK2;
output[3:0] COMOUT;
output WRCYC;
output [4:1] SEL;
output reg[7:0] SEVEN_SEG_DATA;
output [2:1] DSEL;
output reg[7:0] DSEVEN_SEG_DATA;
output [4:0]CS_COUNTER;
// output ONFRAME
// output PFRAME;
//internal resister//
//reg STAT[3:0];
reg nframe;
reg [24:0] sec_cnt ;
reg sec1_flag ;//1秒のフラグ
reg toggle_flag ; //1秒ごとにトグルするフラグ
reg [24:0] sec_cnt2 ;
reg sec1_flag2 ;//1秒のフラグ
reg toggle_flag2 ; //1秒ごとにトグルするフラグ
reg sw1;
//reg AD[15:0];
reg[5:0] sw1_counter;
reg[15:0] rcounter_reg;
reg[16:0] rcounter;
reg[16:0] cn;
reg[3:0] com_reg;
wire[3:0] COMOUT;
reg Wrcyc;
reg[7:0] seven_seg1_hold;
reg[7:0] seven_seg2_hold;
reg[7:0] seven_seg3_hold;
reg[7:0] seven_seg4_hold;
reg[7:0] seven_seg_data;
reg[4:1]sel;
reg[1:0]enable_seg;
reg[2:1]dsel;
reg denable_seg;
reg[7:0] dseven_seg1_hold;
reg[7:0] dseven_seg2_hold;
reg tar;
reg[4:0] cs_counter;
// initial nframe <= 1'b1 ;
//parameter F14M7456_cnt=24'h708000 ;//0.5sec interval
//parameter F14M7456_cnt=24'h0FFFFF ;//0.07sec interval
//parameter F14M7456_cnt=24'h168000 ;//0.1sec interval
// parameter F14M7456_cnt=32'h00B4000 ;//0.05sec interval inputting clk: at 14.756Mhz
// parameter F14M7456_cnt=32'h0024000 ;//0.01sec interval
//parameter F14M7456_cnt2=24'h003999 ; //0.001sec interval
parameter F14M7456_cnt=24'h003999 ; //0.001sec interval
parameter F14M7456_cnt2=24'h0005C2 ; //0.0001sec interval
//parameter F14M7456_cnt=32'h0000002E1 ; //0.000005sec interval 10kHz
parameter selinit_value = 4'b0001 ;
parameter dselinit_value =2'b01;
parameter sw1init_value =1'b1;
// parameter selinit_value = 4'b1000 ;
// initial rcounter_reg = 16'b10000000000000000;
// initial SCK = 16'b0000;
initial cs_counter = 5'b00000;
initial nframe <= 1'b1 ;
//***chattring rejection***//
//***The end of chattring rejection***//
always@(posedge CLK)
begin
if(sec_cnt == F14M7456_cnt) begin
sec_cnt <= 24'h000000 ; //counter counting up to the parameter(refer to No 52th row)
sec1_flag <= 1'b1;
end else begin
sec_cnt <= sec_cnt + 1 ;
sec1_flag <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag == 1'b1 )begin
toggle_flag <= !toggle_flag ;
end
end
assign SCK =!toggle_flag;
assign NSCK =toggle_flag;
// assign NSCK =toggle_flag;
always@(posedge CLK)
begin
if(sec_cnt2 == F14M7456_cnt2) begin
sec_cnt2 <= 24'h000000 ; //counter counting up to the parameter(refer to No 52th row)
sec1_flag2 <= 1'b1;
end else begin
sec_cnt2 <= sec_cnt2 + 1 ;
sec1_flag2 <= 1'b0 ;
end
end
always@(posedge CLK)
begin
if(sec1_flag2 == 1'b1 )begin
toggle_flag2 <= !toggle_flag2 ;
end
end
assign SCK2 =!toggle_flag2;
always@(posedge NSCK or negedge RST)
begin
if(RST ==1'b0)begin
sw1_counter <= 5'b00000;
end else begin
sw1_counter <= sw1_counter +1'b1;
end
end
always@(posedge CLK)
begin
if(sw1_counter ==0)begin
sw1 <= SW1;
end
end
//NFRAME to nframe Once NFRAME is Low , hold the state.//
assign NFRAME = nframe;
// RCOUNTER
always@(posedge SCK or negedge RST or posedge nframe)
begin
if(RST == 1'b0 ) begin
rcounter_reg <= 16'h0 ;
end else if(nframe ==1'b1)begin
rcounter_reg <= 16'h0 ;
end else begin
rcounter_reg <= rcounter_reg <<1;
rcounter_reg [0] <= rcounter[16];
end
end
always@*
begin
rcounter[16] <= ~|rcounter_reg;
rcounter[15:0]<=rcounter_reg;
cn<=~rcounter;
end
assign NRCOUNTER = cn;
always@(negedge RST or negedge sw1 or posedge cs_counter[4] )
begin
if( RST == 1'b0)begin
nframe <= 1'b1;
end else if(cs_counter[4] == 1'b1)begin
nframe <= 1'b1;
end else begin
nframe <=1'b0;
end
end
always@(posedge NSCK or negedge RST )//SCK
begin
if(RST == 1'b0 )begin
cs_counter<= 5'b00000;
end else if(cs_counter == 5'b10001)begin
cs_counter <=5'b00000;
end else if(sw1 ==1'b0)
begin
cs_counter <= cs_counter +1'b1;
end else begin
cs_counter <=5'b00000;
end
end
assign CS_COUNTER = cs_counter;
always@( negedge RST or negedge SW1 or posedge LADCOM[3:0] or posedge CLK or negedge SCK or negedge cn[0] )
begin if(RST ==1'b0)begin
com_reg <=1'b0;
end else if(cn[0]==1'b0 )begin
if(SCK ==1'b1)
case(LADCOM)
4'b0000 : com_reg<= 1'b0; //'0'
4'b0001 : com_reg <= 1'b0; //'1'
4'b0010 : com_reg <= 1'b0; //'1'
4'b0011 : com_reg<= 1'b0; //'0'
4'b0100 : com_reg<= 1'b0 ; //'0'
4'b0101 : com_reg <= 1'b0; //'1'
4'b0110 : com_reg<= 1'b0; //'0'
4'b0111 : com_reg<= 1'b0 ; //'0'
4'b1000 : com_reg<= 1'b0 ; //'0'
4'b1001 : com_reg <= 1'b0; //'1'
4'b1010 : com_reg<= 1'b0; //'0'
4'b1011 : com_reg<= 1'b0 ; //'0'
4'b1100 : com_reg<= 1'b0 ; //'0'
4'b1101 : com_reg<= 1'b0 ; //'0'
4'b1110 : com_reg <= 1'b0; //'1'
4'b1111 : com_reg<= 1'b1; //'0'
default: com_reg<= 1'b0 ; //'0'
endcase
end
end
assign COMOUT =com_reg;
always@( negedge RST or negedge SW1 or posedge LADCOM[3:0] or posedge CLK or negedge SCK or negedge cn[1] )
begin if(RST ==1'b0)begin
Wrcyc <=1'b0;
end else if(cn[1]==1'b0 )begin
if(SCK ==1'b1)
case(LADCOM)
4'b0000 : Wrcyc<= 1'b0; //'0'
4'b0001 : Wrcyc <= 1'b0; //'1'
4'b0010 : Wrcyc <= 1'b1; //'1'
4'b0011 : Wrcyc<= 1'b1; //'0'
4'b0100 : Wrcyc<= 1'b0 ; //'0'
4'b0101 : Wrcyc <= 1'b0; //'1'
4'b0110 : Wrcyc<= 1'b0; //'0'
4'b0111 : Wrcyc<= 1'b0 ; //'0'
4'b1000 : Wrcyc<= 1'b0 ; //'0'
4'b1001 : Wrcyc <= 1'b0; //'1'
4'b1010 : Wrcyc<= 1'b0; //'0'
4'b1011 : Wrcyc<= 1'b0 ; //'0'
4'b1100 : Wrcyc<= 1'b0 ; //'0'
4'b1101 : Wrcyc<= 1'b0 ; //'0'
4'b1110 : Wrcyc <= 1'b0; //'1'
4'b1111 : Wrcyc<= 1'b1; //'0'
default: Wrcyc<= 1'b0 ; //'0'
endcase
end
end
always@( negedge RST or negedge SW1 or posedge LADCOM[3:0] or posedge CLK or negedge SCK or negedge cn[1] )
begin if(RST ==1'b0)begin
tar <=1'b0;
end else if(cn[1]==1'b0 )begin
if(SCK ==1'b1)
case(LADCOM)
4'b0000 : tar<= 1'b0; //'0'
4'b0001 : tar <= 1'b0; //'1'
4'b0010 : tar <= 1'b0; //'1'
4'b0011 : tar<= 1'b0; //'0'
4'b0100 : tar<= 1'b0 ; //'0'
4'b0101 : tar <= 1'b0; //'1'
4'b0110 : tar<= 1'b0; //'0'
4'b0111 : tar<= 1'b0 ; //'0'
4'b1000 : tar<= 1'b0 ; //'0'
4'b1001 : tar <= 1'b0; //'1'
4'b1010 : tar<= 1'b0; //'0'
4'b1011 : tar<= 1'b0 ; //'0'
4'b1100 : tar<= 1'b0 ; //'0'
4'b1101 : tar<= 1'b0 ; //'0'
4'b1110 : tar <= 1'b0; //'1'
4'b1111 : tar<= 1'b1; //'0'
default: tar<= 1'b0 ; //'0'
endcase
end
end
assign WRCYC =Wrcyc;
always@(posedge SCK2 or negedge RST)begin
if(RST == 1'b0 )begin
sel <= selinit_value;
end else begin
sel[4] <= sel[1] ; //シフト動作を開始する
sel[3] <= sel[4] ; //シフト動作を開始する
sel[2] <= sel[3] ; //シフト動作を開始する
sel[1] <= sel[2] ;
end
end
assign SEL[4:1] = ~sel[4:1];
always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[2] or posedge SCK)
begin if(RST ==1'b0)begin
seven_seg1_hold <=8'b00000110;
end else if(cn[2]==1'b0 )begin
if(SCK ==1'b1&& WRCYC==1'b1 && COMOUT==1'b1)
case(LADCOM)
4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0' dot g f e d c b a
4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1'
4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2'
4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3'
4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4'
4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5'
4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6'
4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7'
4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8'
4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9'
4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A'
4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b'
4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c'
4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d'
4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E'
4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F'
default: seven_seg1_hold <= 8'b00000110;
endcase
end
end
always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[3] or posedge SCK)
begin if(RST ==1'b0)begin
seven_seg2_hold <=8'b00000110;
end else if(cn[3]==1'b0)begin
if(SCK ==1'b1&& WRCYC==1'b1 && COMOUT==1'b1)
case(LADCOM)
4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0
4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1'
4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2'
4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3'
4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4'
4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5'
4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6'
4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7'
4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8'
4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9'
4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A'
4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b'
4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c'
4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d'
4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E'
4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F'
default: seven_seg2_hold <= 8'b00000110;
endcase
end
end
always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[4] or posedge SCK)
begin if(RST ==1'b0)begin
seven_seg3_hold <=8'b00000110;
end else if(cn[4]==1'b0)begin
if(SCK ==1'b1&& WRCYC==1'b1 && COMOUT==1'b1)
case(LADCOM)
4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0'
4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1'
4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2'
4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3'
4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4'
4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5'
4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6'
4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7'
4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8'
4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9'
4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A'
4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b'
4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c'
4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d'
4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E'
4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F'
default: seven_seg3_hold <= 8'b00000110;
endcase
end
end
always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[5] or posedge SCK)
begin if(RST ==1'b0)begin
seven_seg4_hold <=8'b00000110;
end else if(cn[5]==1'b0)begin
if(SCK ==1'b1&& WRCYC==1'b1 && COMOUT==1'b1)
case(LADCOM)
4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0'
4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1'
4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2'
4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3'
4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4'
4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5'
4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6'
4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7'
4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8'
4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9'
4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A'
4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b'
4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c'
4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d'
4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E'
4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F'
default: seven_seg4_hold <= 8'b00000110;
endcase
end
end
always@(posedge SCK2 or negedge RST)begin
if(RST == 1'b0 )begin
enable_seg <= 2'b00;
end else begin
enable_seg <= enable_seg +1'b1;
end
end
always@* //* whenever inputs change, holding counter value as the resister "SEVEN_SEG_DATA"
begin
case(enable_seg)
2'b00: SEVEN_SEG_DATA <= ~seven_seg4_hold;
2'b01: SEVEN_SEG_DATA<=~seven_seg1_hold;
2'b10: SEVEN_SEG_DATA<=~seven_seg2_hold;
2'b11: SEVEN_SEG_DATA<=~seven_seg3_hold;
default SEVEN_SEG_DATA<=8'b11111111;
endcase
end
always@(negedge RST or posedge SCK2)
begin if(RST == 1'b0 )begin
dsel <= dselinit_value;
end else begin
dsel[2]<=dsel[1] ; //シフト動作を開始する
dsel[1] <= dsel[2] ; //シフト動作を開始する
end
end
assign DSEL[2:1] =~dsel[2:1];
always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[6] or posedge SCK)
begin if(RST ==1'b0)begin
dseven_seg1_hold <=8'b00000110;
end else if(cn[6]==1'b0 )begin
if(SCK ==1'b1&& WRCYC==1'b1 && COMOUT==1'b1)
case(LADCOM)
4'b0000 : dseven_seg1_hold<= 8'b00111111 ; //'0' dot g f e d c b a
4'b0001 : dseven_seg1_hold <= 8'b00000110 ; //'1'
4'b0010 : dseven_seg1_hold<= 8'b01011011 ; //'2'
4'b0011 : dseven_seg1_hold <= 8'b01001111 ; //'3'
4'b0100 : dseven_seg1_hold <= 8'b01100110 ; //'4'
4'b0101 : dseven_seg1_hold <= 8'b01101101 ; //'5'
4'b0110 : dseven_seg1_hold <= 8'b01111101 ; //'6'
4'b0111 : dseven_seg1_hold <= 8'b00100111 ; //'7'
4'b1000 : dseven_seg1_hold <= 8'b01111111 ; //'8'
4'b1001 : dseven_seg1_hold <= 8'b01101111 ; //'9'
4'b1010 : dseven_seg1_hold <= 8'b01110111 ; //'A'
4'b1011 : dseven_seg1_hold <= 8'b01111100 ; //'b'
4'b1100 : dseven_seg1_hold <= 8'b01011000 ; //'c'
4'b1101 : dseven_seg1_hold <= 8'b01011110 ; //'d'
4'b1110 : dseven_seg1_hold <= 8'b01111001 ; //'E'
4'b1111 : dseven_seg1_hold <= 8'b01110001 ; //'F'
default: dseven_seg1_hold <= 8'b00000110;
endcase
end
end
always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[7] or posedge SCK)
begin if(RST ==1'b0)begin
dseven_seg2_hold <=8'b00000110;
end else if(cn[7]==1'b0)begin
if(SCK ==1'b1&& WRCYC==1'b1 && COMOUT==1'b1)
case(LADCOM)
4'b0000 : dseven_seg2_hold<= 8'b00111111 ; //'0
4'b0001 : dseven_seg2_hold <= 8'b00000110 ; //'1'
4'b0010 : dseven_seg2_hold<= 8'b01011011 ; //'2'
4'b0011 : dseven_seg2_hold <= 8'b01001111 ; //'3'
4'b0100 : dseven_seg2_hold <= 8'b01100110 ; //'4'
4'b0101 : dseven_seg2_hold <= 8'b01101101 ; //'5'
4'b0110 : dseven_seg2_hold <= 8'b01111101 ; //'6'
4'b0111 : dseven_seg2_hold <= 8'b00100111 ; //'7'
4'b1000 : dseven_seg2_hold <= 8'b01111111 ; //'8'
4'b1001 : dseven_seg2_hold <= 8'b01101111 ; //'9'
4'b1010 : dseven_seg2_hold <= 8'b01110111 ; //'A'
4'b1011 : dseven_seg2_hold <= 8'b01111100 ; //'b'
4'b1100 : dseven_seg2_hold <= 8'b01011000 ; //'c'
4'b1101 : dseven_seg2_hold <= 8'b01011110 ; //'d'
4'b1110 : dseven_seg2_hold <= 8'b01111001 ; //'E'
4'b1111 : dseven_seg2_hold <= 8'b01110001 ; //'F'
default: dseven_seg2_hold <= 8'b00000110;
endcase
end
end
always@(posedge SCK2 or negedge RST)begin
if(RST == 1'b0 )begin
denable_seg <= 1'b0;
end else begin
denable_seg <= denable_seg +1'b1;
end
end
always@* //* whenever inputs change, holding counter value as the resister "SEVEN_SEG_DATA"
begin
case(denable_seg)
1'b0: DSEVEN_SEG_DATA <= ~dseven_seg2_hold;
1'b1: DSEVEN_SEG_DATA<=~dseven_seg1_hold;
default DSEVEN_SEG_DATA<=8'b11111111;
endcase
end
endmodule
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