./DAC_SPI2
./DAC_SPI2_24
./PORT80h translator1_1_570
./7seg¥À¥¤¥Ê¥ß¥Ã¥¯ÅÀÅô
./SPI_read1
./PWM_SYNC2
./nand_controller
./nand_controller2
./DE0-CV
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?: ¾ò·ï?¿¿¤Î¾ì¹ç¤Î·ë²Ì:µ¶¤Î¾ì¹ç¤Î·ë²Ì ~ ¢£Îã assign DOUT =(EN=0)? DIN:8'hz; °ÕÌ£¡§¤â¤·EN=0 ¤Ç¤¢¤Ã¤¿¤éDIN¤òDOUT¤ËÂåÆþ¤¹¤ë¡£¤½¤¦¤Ç¤Ê¤¤¤È¤¤Ï¡¢¥Ï¥¤¥¤¥ó¥Ô¡¼¥À¥ó¥¹¤È¤¹¤ë¡£ Ï¢ÀÜ {,} Æó¤Ä°Ê¾å¤Î¥ª¥Ú¥é¥ó¥É¤ò¤Ò¤È¤Ä¤Î¥Ó¥Ã¥Èɽ¸½¤Ë¤Þ¤È¤á¤ë
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reg [15:0] data_reg; wire [15:0] DATA; assign DATA = data_reg; //data_reg ¤ÏÆâÉô¥ì¥¸¥¹¥¿ DATA¤Ï¼Âºß¤Î¿®¹æ
//¥Õ¥ë¥¢¥À¡¼ module fulladd(A,B,CIN,Q,COUT); input A,B,CIN; output Q,COUT; assign Q = A ^ B ^ CIN; assign COUT = ( A + B )|( B & CIN)|(CIN & A); endmodule
module led_onoff2( //¥â¥¸¥å¡¼¥ëÀë¸À¤Î³«»Ï SW1_I , //¥Ý¡¼¥ÈÄêµÁ¤½¤Î1 LED1_O //¥Ý¡¼¥ÈÄêµÁ¤½¤Î2 ); //*******************************************************// //Àë¸À¤·¤¿¥Ý¡¼¥È¤Ë¿®¹æ°À¤òÍ¿¤¨¤ë input SW1_I ; //¥¹¥¤¥Ã¥ÁÆþÎÏ output LED1_O ;//LED½ÐÎÏ //***ÆâÉô¥Î¡¼¥É******************************************// reg led_status ; //***ÆâÉô²óÏ©********************************************// always @(posedge SW1_I) begin begin led_status <= !led_status ; //¥ì¥¸¥¹¥¿½ÐÎϤÎȿžÃͤòÂåÆþ¤¹¤ë end end assign LED1_O = !led_status ; //LED¤Ø¤Î½ÐÎÏ endmodule
¡¦constrain file¤Îµ½Ò
# NET "SW1_I" LOC="P30"; NET "LED1_O" LOC="P17"; NET "SW1_I" CLOCK_DEDICATED_ROUTE = FALSE; //¥¿¥¤¥ß¥ó¥°¥¨¥é¡¼ËÉ»ß #
module led_onoff4( reset_i , switch_i , led_o ); //***********************Æþ½ÐÎÏ¥Ô¥óÄêµÁ************************// input reset_i ; //¥ê¥»¥Ã¥ÈÆþÎÏ input switch_i ; //¥¹¥¤¥Ã¥ÁÆþÎÏ output [4:1] led_o ; //LED½ÐÎÏ //***********************ÆâÉô¥Î¡¼¥É****************************// parameter init_value = 4'b0001 ; //½é´üÃÍ reg [4:1] led_status ; //**********************ÆâÉô²óÏ©*****************************// always@(posedge switch_i or posedge reset_i) begin if ( reset_i == 1'b1 ) begin led_status <= init_value ; end else begin /************º¸¥í¡¼¥Æ¡¼¥È********************/ led_status[1] <= led_status[4] ; //¥·¥Õ¥ÈÆ°ºî¤ò³«»Ï¤¹¤ë led_status[2] <= led_status[1] ; //¥·¥Õ¥ÈÆ°ºî¤ò³«»Ï¤¹¤ë led_status[3] <= led_status[2] ; //¥·¥Õ¥ÈÆ°ºî¤ò³«»Ï¤¹¤ë led_status[4] <= led_status[3] ; //¥·¥Õ¥ÈÆ°ºî¤ò³«»Ï¤¹¤ë end end assign led_o[4:1] = ‾led_status[4:1] ; //LED¤Ø¤Î½ÐÎÏ endmodule
¡¦constrain file¤Îµ½Ò # NET "led_o[4]" LOC="P23"; NET "led_o[3]" LOC="P22"; NET "led_o[2]" LOC="P18"; NET "led_o[1]" LOC="P17"; NET "switch_i" LOC="P27"; NET "reset_i" LOC="P30"; NET "switch_i" CLOCK_DEDICATED_ROUTE = FALSE; NET "reset_i" CLOCK_DEDICATED_ROUTE = FALSE; #
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LED4 | LED3 | LED2 | LED1 |
¾ÃÅô | ÅÀÅô | ¾ÃÅô | ÅÀÅô |
module led_onoff5( reset, switch, led_n ); //******Æþ½ÐÎÏ¥Ô¥óÄêµÁ******// input reset ; //¥ê¥»¥Ã¥ÈÆþÎÏ input switch ; //¥¹¥¤¥Ã¥ÁÆþÎÏ output[4:1] led_n ; //LED½ÐÎÏ //******ÆâÉô¥Î¡¼¥É******// reg [3:0] counter4 ; //******ÆâÉô²óÏ©******// // //¥«¥¦¥ó¥¿Éô // always@(posedge switch or posedge reset) begin if ( reset == 1'b1 ) begin counter4 <= 4'b0000 ; end else begin counter4 <= counter4 + 1 ;//counter¤Ë1¤º¤Ä²Ã¤¨¤Æ¤¤¤¯ end end // //LEDɽ¼¨Éô // assign led_n[4] = !counter4[3] ; assign led_n[3] = !counter4[2] ; assign led_n[2] = !counter4[1] ; assign led_n[1] = !counter4[0] ; endmodule
¡¦constrainfile¤Îµ½Ò # NET "led_n[4]" LOC="P23"; NET "led_n[3]" LOC="P22"; NET "led_n[2]" LOC="P18"; NET "led_n[1]" LOC="P17"; NET "reset" LOC="P27"; NET "switch" LOC="P30"; NET "reset" CLOCK_DEDICATED_ROUTE = FALSE; NET "switch" CLOCK_DEDICATED_ROUTE = FALSE; #
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module led_onoff_7seg( reset , switch, seg7_oe_n, seg7_n ); //******Æþ½ÐÎÏ******// input reset ; input switch ; output [4:1] seg7_oe_n ; output [8:1] seg7_n ; //******ÆâÉô¥Î¡¼¥É******// reg[3:0] counter4 ; reg[7:0] reg_seg7 ; //******ÆâÉô²óÏ©******// // //¥«¥¦¥ó¥¿Éô // always@(posedge switch or posedge reset) begin if(reset == 1'b1 ) begin counter4 <= 4'b0000 ; end else begin counter4 <= counter4 + 1 ; end end // //7¥»¥°¥á¥ó¥Èɽ¼¨Éô // assign seg7_oe_n = 4'b1110 ; //ºÇ²¼°Ì·å¤Î¤ßɽ¼¨¤ò͸ú¤Ë¤¹¤ë always@(posedge switch) begin case(counter4) 4'b0000 : reg_seg7 <= 8'b10111111 ; //'0'¤òɽ¼¨ 4'b0001 : reg_seg7 <= 8'b00000110 ; //'1'¤òɽ¼¨ 4'b0010 : reg_seg7 <= 8'b11011011 ; //'2'¤òɽ¼¨ 4'b0011 : reg_seg7 <= 8'b01001111 ; //'3'¤òɽ¼¨ 4'b0100 : reg_seg7 <= 8'b11100110 ; //'4'¤òɽ¼¨ 4'b0101 : reg_seg7 <= 8'b01101101 ; //'5'¤òɽ¼¨ 4'b0110 : reg_seg7 <= 8'b11111101 ; //'6'¤òɽ¼¨ 4'b0111 : reg_seg7 <= 8'b00100111 ; //'7'¤òɽ¼¨ 4'b1000 : reg_seg7 <= 8'b11111111 ; //'8'¤òɽ¼¨ 4'b1001 : reg_seg7 <= 8'b01101111 ; //'9'¤òɽ¼¨ 4'b1010 : reg_seg7 <= 8'b11110111 ; //'A'¤òɽ¼¨ 4'b1011 : reg_seg7 <= 8'b01111100 ; //'b'¤òɽ¼¨ 4'b1100 : reg_seg7 <= 8'b11011000 ; //'c'¤òɽ¼¨ 4'b1101 : reg_seg7 <= 8'b01011110 ; //'d'¤òɽ¼¨ 4'b1110 : reg_seg7 <= 8'b11111001 ; //'E'¤òɽ¼¨ 4'b1111 : reg_seg7 <= 8'b01110001 ; //'F'¤òɽ¼¨ endcase end assign seg7_n = ~reg_seg7 ; endmodule
¡¦constrain file¤Îµ½Ò
# NET "seg7_oe_n[4]" LOC="P2"; NET "seg7_oe_n[3]" LOC="P3"; NET "seg7_oe_n[2]" LOC="P85"; NET "seg7_oe_n[1]" LOC="P86"; NET "seg7_n[8]" LOC="P95"; NET "seg7_n[7]" LOC="P91"; NET "seg7_n[6]" LOC="P90"; NET "seg7_n[5]" LOC="P70"; NET "seg7_n[4]" LOC="P71"; NET "seg7_n[3]" LOC="P98"; NET "seg7_n[2]" LOC="P92"; NET "seg7_n[1]" LOC="P94"; NET "reset" LOC="P30"; NET "switch" LOC="P27"; NET "reset" CLOCK_DEDICATED_ROUTE = FALSE; NET "switch" CLOCK_DEDICATED_ROUTE = FALSE; #
module LEDLIGHT( CLK, LED_out ); /**********************/ input CLK ; output LED_out ; wire LED_out ; /**********************/ parameter F33M000_cnt=32'h00fbc520 ;//0.5É䴤ȤÎÊѲ½ reg [31:0] sec_cnt ;//£±ÉúîÀ®ÍÑ¥«¥¦¥ó¥¿ reg sec1_flag ;//1ÉäΥե饰 reg toggle_flag ; //1É䴤Ȥ˥ȥ°¥ë¤¹¤ë¥Õ¥é¥° /**********************/ /*1ÉÃ¥«¥¦¥ó¥¿Éô */ /**********************/ always@(posedge CLK) begin if(sec_cnt == F33M000_cnt) begin //¤â¤·3300Ëü²ó¿ô¤¨¤¿¤é¥«¥¦¥ó¥¿¤ò¥ê¥»¥Ã¥È¤¹¤ë sec_cnt <= 32'h00000000 ; sec1_flag <= 1'b1; //SEC1_FLAG¤Ë1¤ò¥»¥Ã¥È¤¹¤ë end else begin sec_cnt <= sec_cnt + 1 ; sec1_flag <= 1'b0 ; end end /**********************/ /*1Éø¡½ÐÉô */ /**********************/ always@(posedge CLK) begin if(sec1_flag == 1'b1 )begin toggle_flag <= !toggle_flag ; end end /**********************/ /*LED½ÐÎÏÉô */ /**********************/ assign LED_out = toggle_flag ; /**********************/ endmodule
¡¦constrain file ¤Îµ½Ò
# NET "CLK" LOC="P63"; NET "LED_out" LOC="P17"; NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; NET "LED_out" CLOCK_DEDICATED_ROUTE = FALSE; #
module top( reset, clk, seg7_oe_n, seg7_n, led_n ); //******Æþ½ÐÎÏÄêµÁ***************************************************************// input reset ; input clk ; output[4:1] seg7_oe_n ; output[4:1] led_n ; output[8:1] seg7_n ; //******ÆâÉô¥Î¡¼¥É*****************************************************************// wire sec1 ; reg [3:0] counter4 ; wire [7:0] wire_seg7 ; //******ÆâÉô²óÏ©*****************************************************************// //1ÉÃ¥¿¥¤¥ß¥ó¥°À¸À® //²¼°Ì¥â¥¸¥å¡¼¥ë¤È¤·¤Æ1ÉÃ¥«¥¦¥ó¥¿¤òÀܳ¤¹¤ë pulse1sec U_pulse1sec( .clk(clk), .reset(reset), .sec1(sec1) ); //¥«¥¦¥ó¥¿Éô always@(posedge clk or posedge reset) begin if( reset == 1'b1 )begin counter4 <= 4'b0000 ; end else begin if ( sec1 == 1'b1 )begin counter4 <= counter4 + 1 ; end end end assign led_n = ~counter4 ; //7¥»¥°¥á¥ó¥Èɽ¼¨Éô //²¼°Ì¥â¥¸¥å¡¼¥ë¤È¤·¤Æ7¥»¥°¥á¥ó¥È¥Ç¥³¡¼¥À¤òÀܳ¤¹¤ë seg7enc U_seg7enc ( .hex4_in (counter4), //²¼°Ì¤Î¿®¹æ̾(¾å°Ì¤Î¿®¹æ̾) .seg7_out(wire_seg7) ) ; assign seg7_n = ~wire_seg7; assign seg7_oe_n = 4'b0000 ; endmodule
¡¦2-7 7segɽ¼¨/sec_²¼°Ì¥â¥¸¥å¡¼¥ë ¡¦pulse1sec
module pulse1sec( clk, reset, sec1 ); input clk ; input reset ; output sec1 ; //************ÆâÉô¥Î¡¼¥É****************************************************************// //1ÉÃ¥«¥¦¥ó¥¿¥Î¡¼¥É parameter [31:0] param_1Second = 32'h01F78A40 ; //1ÉÃ´Ö reg [31:0] Sec1_counter ; //1Éô֤ò¥«¥¦¥ó¥È¤¹¤ë¡£ reg Pulse_1Sec ; //Sec1_counter¤¬1Éô֤ˤʤ俤顢¥Ó¥Ã¥Èȿž¤¹¤ë¡£ //1ÉÃ¥¿¥¤¥ß¥ó¥°À¸À® always@(posedge clk or posedge reset) begin if( reset == 1'b1 ) begin Sec1_counter <= 32'b0 ; Pulse_1Sec <= 1'b0 ; end else begin if ( Sec1_counter == param_1Second ) begin Pulse_1Sec <= 1'b1 ; Sec1_counter <= 32'b0 ; end else begin Pulse_1Sec <= 1'b0 ; Sec1_counter <= Sec1_counter + 1 ; end end end assign sec1 = Pulse_1Sec ;
endmodule
¡¦2-7 7segɽ¼¨/sec_²¼°Ì¥â¥¸¥å¡¼¥ë ¡¦seg7enc
module seg7enc( hex4_in , //4¥Ó¥Ã¥È¥Ç¡¼¥¿ÆþÎÏ seg7_out //7¥»¥°¥á¥ó¥Èɽ¼¨¥Ñ¥¿¡¼¥ó ); input [3:1] hex4_in ; output [7:1] seg7_out ; //*****ÆâÉô¥Î¡¼¥É*********// reg [7:1] reg_seg7 ; //*****ÆâÉô²óÏ©*********// always @* begin case(hex4_in) //¾å°Ìcounter4¤ÎÃͤÇɽ¼¨¤òÀÚ¤êÂؤ¨¤ë 4'b0000 : reg_seg7 <= 8'b10111111 ; //'0'¤òɽ¼¨ 4'b0001 : reg_seg7 <= 8'b00000110 ; //'1'¤òɽ¼¨ 4'b0010 : reg_seg7 <= 8'b11011011 ; //'2'¤òɽ¼¨ 4'b0011 : reg_seg7 <= 8'b01001111 ; //'3'¤òɽ¼¨ 4'b0100 : reg_seg7 <= 8'b11100110 ; //'4'¤òɽ¼¨ 4'b0101 : reg_seg7 <= 8'b01101101 ; //'5'¤òɽ¼¨ 4'b0110 : reg_seg7 <= 8'b11111101 ; //'6'¤òɽ¼¨ 4'b0111 : reg_seg7 <= 8'b00100111 ; //'7'¤òɽ¼¨ 4'b1000 : reg_seg7 <= 8'b11111111 ; //'8'¤òɽ¼¨ 4'b1001 : reg_seg7 <= 8'b01101111 ; //'9'¤òɽ¼¨ 4'b1010 : reg_seg7 <= 8'b11110111 ; //'A'¤òɽ¼¨ 4'b1011 : reg_seg7 <= 8'b01111100 ; //'b'¤òɽ¼¨ 4'b1100 : reg_seg7 <= 8'b11011000 ; //'c'¤òɽ¼¨ 4'b1101 : reg_seg7 <= 8'b01011110 ; //'d'¤òɽ¼¨ 4'b1110 : reg_seg7 <= 8'b11111001 ; //'E'¤òɽ¼¨ 4'b1111 : reg_seg7 <= 8'b01110001 ; //'F'¤òɽ¼¨ endcase end assign seg7_out = reg_seg7 ; endmodule
¡¦constrain file
# NET "seg7_oe_n[4]" LOC="P2"; NET "seg7_oe_n[3]" LOC="P3"; NET "seg7_oe_n[2]" LOC="P85"; NET "seg7_oe_n[1]" LOC="P86"; NET "seg7_n[8]" LOC="P95"; NET "seg7_n[7]" LOC="P91"; NET "seg7_n[6]" LOC="P90"; NET "seg7_n[5]" LOC="P70"; NET "seg7_n[4]" LOC="P71"; NET "seg7_n[3]" LOC="P98"; NET "seg7_n[2]" LOC="P92"; NET "seg7_n[1]" LOC="P94"; NET "reset" LOC="P30"; NET "clk" LOC="P63"; #
module TIM180( //ÆþÎÏ¥Ô¥ó CLK_I, SW_START_I, SW_RESET_I, //½ÐÎÏ¥Ô¥ó SEG_O, DP1OEN_O, DP2OEN_O, DP3OEN_O, DP4OEN_O, LED1_O, LED2_O, LED3_O, LED4_O ); //Æþ½ÐÎÏ¥Ô¥ó¤ÎÄêµÁ input CLK_I ; input SW_START_I; input SW_RESET_I; output reg[8:1] SEG_O; output DP1OEN_O ; output DP2OEN_O ; output DP3OEN_O ; output DP4OEN_O ; output LED1_O ; output LED2_O ; output LED3_O ; output LED4_O ; //ÆâÉô²óÏ©ÍѤΥ쥸¥¹¥¿Àë¸À parameter[31:0] param_1Second = 32'h01F78A40 ; reg[31:0] Sec1_counter ; reg[19:0] OEN_counter ; reg[3:0] TIM_3 ;//100ÉÃ¥¿¥¤¥Þ reg[3:0] TIM_2 ;//10ÉÃ¥¿¥¤¥Þ reg[3:0] TIM_1 ;//1ÉÃ¥¿¥¤¥Þ reg[7:0] node_SEG3 ;//7¥»¥°¥á¥ó¥ÈLEDɽ¼¨ÍÑÆâÉô¥Î¡¼¥É reg[7:0] node_SEG2 ;//7¥»¥°¥á¥ó¥ÈLEDɽ¼¨ÍÑÆâÉô¥Î¡¼¥É reg[7:0] node_SEG1 ;//7¥»¥°¥á¥ó¥ÈLEDɽ¼¨ÍÑÆâÉô¥Î¡¼¥É reg Pulse_1Sec ; reg TIM_START ; reg TIMEOUT ; wire [1:0] OE_DIGIT ; reg [4:1] SEGEN_O ; //¥¿¥¤¥Þ¶îÆ°³«»Ï¥Õ¥é¥°// always@(posedge CLK_I) begin if(SW_RESET_I == 1'b1 )begin //¥ê¥»¥Ã¥È¥¹¥¤¥Ã¥Á¤¬²¡¤µ¤ì¤¿¤é TIM_START <= 1'b0 ;//TIM_START¥Õ¥é¥°¤ò0¤Ø¥»¥Ã¥È¤¹¤ë end else begin if(SW_START_I == 1'b1 )begin//¥¹¥¿¡¼¥È¥¹¥¤¥Ã¥Á¤¬²¡¤µ¤ì¤¿¤é TIM_START <= 1'b1 ;//TIM_START¥Õ¥é¥°¤ò1¤Ø¥»¥Ã¥È¤¹¤ë end end end //1ÉÃ¥¿¥¤¥ß¥ó¥°À¸À®// always@(posedge CLK_I or posedge SW_RESET_I) begin if(SW_RESET_I == 1'b1)begin Sec1_counter <= 32'b0 ; Pulse_1Sec <= 1'b0 ; end else begin if(TIM_START == 1'b1 )begin //TIM_START¥¿¥¤¥Þ³«»Ï¥Õ¥é¥°¤¬Î©¤Á if(Sec1_counter == param_1Second )begin //Sec1_counter ¤¬1Éô֤ò¥«¥¦¥ó¥È¤·¤¿¤é Pulse_1Sec <= 1'b1 ; //Pulse_1Sec¤Ë1¤òÂåÆþ Sec1_counter <= 32'b0 ; //Sec1_counter ¤ò0¤«¤é¿ô¤¨¤Ê¤ª¤¹ end else begin Pulse_1Sec <= 1'b0 ; //Sec1_counter¤¬1Éô֤ò¥«¥¦¥ó¥È¤·¤Ê¤¤¤Ê¤éPulse£±Sec¤Ï¾ï¤Ë0¤òÂåÆþ Sec1_counter <= Sec1_counter + 1 ; end end end end //180ÉÃ¥¿¥¤¥Þ²óÏ©// always@(posedge CLK_I or posedge SW_RESET_I) begin if(SW_RESET_I == 1'b1)begin TIM_1 <= 4'b0000 ;//0 | TIM_2 <= 4'b1000 ;//8 | TIM_3 <= 4'b0001 ;//1 |--180Éäò¥»¥Ã¥È¤¹¤ë end else begin if(TIMEOUT == 1'b1)begin TIM_1 <= 4'b1111 ; TIM_2 <= 4'b1111 ; TIM_3 <= 4'b1111 ;// Æüì¤ÊÃͤò¥»¥Ã¥È¤¹¤ë end else begin if(Pulse_1Sec == 1'b1)begin//°Ê²¼£±É÷вᤴ¤È¤Î½èÍý //£±ÉÃ¥«¥¦¥ó¥¿Éô if(TIM_1 == 0)begin TIM_1 <=4'b1001 ; end else begin TIM_1 <= TIM_1 - 1 ; //9>>7>6>5>4>3>2>1>0>9 ¤Èɽ¼¨¤òÊѲ½¤µ¤»¤ë end //10ÉÃ¥«¥¦¥ó¥¿Éô if(TIM_1 == 0)begin //1¤Î°Ì¤¬0¤Î¤È¤¤Î¤ß°Ê²¼¤Î½èÍý¤ò¹Ô¤¦ if(TIM_2 == 0)begin //10¤Î°Ì¤â0¤Î¤È¤ TIM_2 <= 4'b1001 ; //9¤ò¥»¥Ã¥È¤¹¤ë end else begin TIM_2 <= TIM_2 - 1 ; //(1¤Î°Ì¤¬0¤Ç)10¤Î°Ì¤¬0°Ê³°¤Î¤È¤ ¥«¥¦¥ó¥È¥À¥¦¥ó¤¹¤ë end end //100ÉÃ¥«¥¦¥ó¥¿Éô if((TIM_1 == 0)&(TIM_2 == 0))begin //1¤Î°Ì¤¬0,10¤Î°Ì¤â0¤Î¤È¤¤Î¤ß°Ê²¼¤Î½èÍý¤ò¹Ô¤¦ if(TIM_3 == 0)begin //100¤Î°Ì¤¬0¤Î¤È¤ TIM_3 <= 4'b1001 ; //100¤Î°Ì¤Ë9¤ò¥»¥Ã¥È¤¹¤ë(180ÉÃ¥»¥Ã¥È¤À¤È¤½¤ó¤Ê¤³¤È¤Ï¤Ê¤¤¤¬) end else begin TIM_3 <= TIM_3 - 1 ; //(1¤Î°Ì¤¬0¤Ç,10¤Î°Ì¤â0¤Ç)100¤Î°Ì¤¬0°Ê³°¤Î¤È¤ ¥«¥¦¥ó¥È¥À¥¦¥ó¤¹¤ë end end end end end end //¥¿¥¤¥à¥¢¥¦¥È¸¡½Ð// always@(posedge CLK_I or posedge SW_RESET_I ) begin if(SW_RESET_I == 1'b1)begin TIMEOUT <= 1'b0 ; end else begin if((TIM_3 == 4'b0000 )&(TIM_2 == 4'b0000 )&(TIM_1 == 4'b0000 )&Pulse_1Sec == 1'b1)begin //ɽ¼¨¤¬000¤Ç¡¢Pulse_1Sec ¤¬1¤Î¤È¤¡Ê1É÷вá¡Ë TIMEOUT <= 1'b1 ; end end end //7¥»¥°¥á¥ó¥ÈLEDɽ¼¨Éô always@(posedge CLK_I) begin case(TIM_3) 4'b0000 : node_SEG3 <= 8'b10111111 ; //'0'¤òɽ¼¨ 4'b0001 : node_SEG3 <= 8'b00000110 ; //'1'¤òɽ¼¨ 4'b0010 : node_SEG3 <= 8'b11011011 ; //'2'¤òɽ¼¨ 4'b0011 : node_SEG3 <= 8'b01001111 ; //'3'¤òɽ¼¨ 4'b0100 : node_SEG3 <= 8'b11100110 ; //'4'¤òɽ¼¨ 4'b0101 : node_SEG3 <= 8'b01101101 ; //'5'¤òɽ¼¨ 4'b0110 : node_SEG3 <= 8'b11111101 ; //'6'¤òɽ¼¨ 4'b0111 : node_SEG3 <= 8'b00100111 ; //'7'¤òɽ¼¨ 4'b1000 : node_SEG3 <= 8'b11111111 ; //'8'¤òɽ¼¨ 4'b1001 : node_SEG3 <= 8'b01101111 ; //'9'¤òɽ¼¨ endcase case(TIM_2) 4'b0000 : node_SEG2 <= 8'b10111111 ; //'0'¤òɽ¼¨ 4'b0001 : node_SEG2 <= 8'b00000110 ; //'1'¤òɽ¼¨ 4'b0010 : node_SEG2 <= 8'b11011011 ; //'2'¤òɽ¼¨ 4'b0011 : node_SEG2 <= 8'b01001111 ; //'3'¤òɽ¼¨ 4'b0100 : node_SEG2 <= 8'b11100110 ; //'4'¤òɽ¼¨ 4'b0101 : node_SEG2 <= 8'b01101101 ; //'5'¤òɽ¼¨ 4'b0110 : node_SEG2 <= 8'b11111101 ; //'6'¤òɽ¼¨ 4'b0111 : node_SEG2 <= 8'b00100111 ; //'7'¤òɽ¼¨ 4'b1000 : node_SEG2 <= 8'b11111111 ; //'8'¤òɽ¼¨ 4'b1001 : node_SEG2 <= 8'b01101111 ; //'9'¤òɽ¼¨ endcase case(TIM_1) 4'b0000 : node_SEG1 <= 8'b10111111 ; //'0'¤òɽ¼¨ 4'b0001 : node_SEG1 <= 8'b00000110 ; //'1'¤òɽ¼¨ 4'b0010 : node_SEG1 <= 8'b11011011 ; //'2'¤òɽ¼¨ 4'b0011 : node_SEG1 <= 8'b01001111 ; //'3'¤òɽ¼¨ 4'b0100 : node_SEG1 <= 8'b11100110 ; //'4'¤òɽ¼¨ 4'b0101 : node_SEG1 <= 8'b01101101 ; //'5'¤òɽ¼¨ 4'b0110 : node_SEG1 <= 8'b11111101 ; //'6'¤òɽ¼¨ 4'b0111 : node_SEG1 <= 8'b00100111 ; //'7'¤òɽ¼¨ 4'b1000 : node_SEG1 <= 8'b11111111 ; //'8'¤òɽ¼¨ 4'b1001 : node_SEG1 <= 8'b01101111 ; //'9'¤òɽ¼¨ endcase end //¥À¥¤¥Ê¥ß¥Ã¥¯ÅÀÅôÊý¼°ÍѤηå»ØÄêÆâÉô¥Î¡¼¥É²óÏ©Éô always@(posedge CLK_I) begin OEN_counter <= OEN_counter + 1 ; end // assign OE_DIGIT = OEN_counter[19:18] ; assign OE_DIGIT = OEN_counter[17:16] ; //OE_DIGIT¤ÎÃͤǡ¢½ÐÎÏÃͤò»þʬ³ä¤ÇSEG_O¤Ë°ú¤ÅϤ¹ always@(posedge CLK_I) begin case(OE_DIGIT) 2'b00: SEG_O <= ‾node_SEG1 ;//node_SEG1(1¤Î°Ì)¤ÎÏÀÍýȿž¤ÇSEG_O¤Ë³ä¤êÅö¤Æ 2'b01: SEG_O <= ‾node_SEG2 ; 2'b10: SEG_O <= ‾node_SEG3 ; default : SEG_O <= ‾(8'b01000000);//¥Ç¥Õ¥©¥ë¥È¤Ï"-"ɽ¼¨¤È¤¹¤ë endcase end //ÅÀÅô¤¹¤ë7¥»¥°É½¼¨Éô(ÉôÉÊ)¤òÁªÂò¤¹¤ë always@(posedge CLK_I) begin case(OE_DIGIT) 2'b00: SEGEN_O <= 4'b0001 ;//1·å¤Îɽ¼¨¥Ç¡¼¥¿¤ò1·å¤Îɽ¼¨Éô¤Øɽ¼¨¤¹¤ë 2'b01: SEGEN_O <= 4'b0010 ; 2'b10: SEGEN_O <= 4'b0100 ; default : SEGEN_O <= 4'b1000;//¥Ç¥Õ¥©¥ë¥È¤Ï1000·åÌÜ͸ú endcase end //ÅÀÅô¤¹¤ë7¥»¥°É½¼¨Éô¤ò»ØÄꤹ¤ë½ÐÎÏ¥Ô¥ó¤Ø½ÐÎÏ»ØÄê¤ò³ä¤êÅö¤Æ¤ë assign DP1OEN_O = !SEGEN_O[1] ;//SEGEN_O¤Î²¼°Ì1bit¤¬1(1·åÌܤÎɽ¼¨Éô¤ò͸ú¤È¤·¤¿¤¤¤È¤)¤ò½ÐÎÏ¥Ô¥ó¤ËÈ¿±Ç¤¹¤ë assign DP2OEN_O = !SEGEN_O[2] ; assign DP3OEN_O = !SEGEN_O[3] ; assign DP4OEN_O = !SEGEN_O[4] ; //LEDɽ¼¨¡¡¥Ç¥Ð¥Ã¥°ÍÑ assign LED1_O =(TIMEOUT == 1'b0)?Sec1_counter[21]:Sec1_counter[24];//¥¿¥¤¥à¥¢¥¦¥È¤·¤Æ¤Ê¤¤ã21bitÌܤòÂåÆþ,¤·¤Æ¤¿¤é24bitÌܤòÂåÆþ 1/8É䴤ȤËÅÀÌÇ assign LED2_O =(TIMEOUT == 1'b0)?Sec1_counter[22]:Sec1_counter[24];//1/4É䴤ȤËÅÀÌÇ assign LED3_O =(TIMEOUT == 1'b0)?Sec1_counter[23]:Sec1_counter[24];//1/2É䴤ȤËÅÀÌÇ assign LED4_O =(TIMEOUT == 1'b0)?Sec1_counter[24]:Sec1_counter[24];//1É䴤ȤËÅÀÌÇ endmodule
¡¦2-8 TIMER180sec.constrainfile
#¡¡¥¯¥í¥Ã¥¯¿®¹æ NET "CLK_I" LOC = "P63" ; #¡¡LED½ÐÎÏ NET "LED1_O" LOC = "P17" ; NET "LED2_O" LOC = "P18" ; NET "LED3_O" LOC = "P22" ; NET "LED4_O" LOC = "P23" ; # ¥¹¥¤¥Ã¥ÁÆþÎÏ NET "SW_RESET_I" LOC = "P30" ; NET "SW_START_I" LOC = "P27" ; #NET "SW3_I" LOC = "P26" ; #NET "SW4_I" LOC = "P24" ; # 7¥»¥°¥á¥ó¥ÈLED¡¦ÅÀÅô͸ú¥é¥¤¥ó NET "DP1OEN_O" LOC = "P86"; NET "DP2OEN_O" LOC = "P85"; NET "DP3OEN_O" LOC = "P3"; NET "DP4OEN_O" LOC = "P2"; # 7¥»¥°¥á¥ó¥ÈLED¡¦³Æ¥¨¥ì¥á¥ó¥ÈLED NET "SEG_O[1]" LOC = "P94"; NET "SEG_O[2]" LOC = "P92"; NET "SEG_O[3]" LOC = "P98"; NET "SEG_O[4]" LOC = "P71"; NET "SEG_O[5]" LOC = "P70"; NET "SEG_O[6]" LOC = "P90"; NET "SEG_O[7]" LOC = "P91"; NET "SEG_O[8]" LOC = "P95";
module DIGCLOCK( //ÆþÎÏ¥Ô¥ó CLK_I, SW_START_I, SW_RESET_I, SW_DispSEC_I, SW_VMAX_I, //½ÐÎÏ¥Ô¥ó SEG_O, DP1OEN_O, DP2OEN_O, DP3OEN_O, DP4OEN_O, LED1_O, LED2_O, LED3_O, LED4_O ); //Æþ½ÐÎÏ¥Ô¥ó¤ÎÄêµÁ input CLK_I ; input SW_START_I ; input SW_RESET_I ; input SW_DispSEC_I ; input SW_VMAX_I ; output reg[8:1] SEG_O ; output DP1OEN_O ; output DP2OEN_O ; output DP3OEN_O ; output DP4OEN_O ; output LED1_O ; output LED2_O ; output LED3_O ; output LED4_O ; //ÆâÉô²óÏ©ÍѤΥ쥸¥¹¥¿Àë¸À parameter[31:0] param_1Second = 32'h01F78A40 ;//33MHz»þ¤Î1ÉÃ¥¿¥¤¥ß¥ó¥° parameter[31:0] param_VMAXsec = 32'h0010C8E0 >>4 ;//33MHz»þ¤Î1/240ÉÃ¥¿¥¤¥ß¥ó¥° >>¤Ï±¦¥·¥Õ¥È4bit reg[31:0] Sec1_counter ; reg[19:0] OEN_counter ; reg[3:0] Count_1sec ; //1ÉÃ¥«¥¦¥ó¥¿ reg[2:0] Count_10sec ; //10ÉÃ¥«¥¦¥ó¥¿ reg[3:0] Count_1min ; //1ʬ¥«¥¦¥ó¥¿ reg[2:0] Count_10min ; //10ʬ¥«¥¦¥ó¥¿ reg[3:0] Count_1hour ; //1»þ¥«¥¦¥ó¥¿ reg Count_10hour ; //10»þ¥«¥¦¥ó¥¿ wire Cnt_1sec_is_9 ; wire Cnt_sec_is_59 ; wire Cnt_1min_is_9 ; wire Cnt_min_is_59 ; wire Cnt_1hour_is_9 ; wire Cnt_hour_is_11 ; wire[3:0] TIM_4 ; wire[3:0] TIM_3 ; wire[3:0] TIM_2 ; wire[3:0] TIM_1 ; reg[7:0] node_SEG4 ; reg[7:0] node_SEG3 ; reg[7:0] node_SEG2 ; reg[7:0] node_SEG1 ; reg CLK_VMAX1 ; reg CLK_VMAX2 ; reg Pulse_1Sec ; reg SEC_Prompt ; reg CLOCK_Start ; wire[1:0] OE_DIGIT ; reg[4:1] SEGEN_O ; //1ÉÃ¥¿¥¤¥ß¥ó¥°// always@(posedge CLK_I or posedge SW_RESET_I) begin if(SW_RESET_I == 1'b1)begin Sec1_counter <= 32'b0 ; Pulse_1Sec <= 1'b0 ; SEC_Prompt <= 1'b0 ; CLOCK_Start <= 1'b0 ; CLK_VMAX1 <= 1'b0 ; CLK_VMAX2 <= 1'b0 ; end else begin if( SW_START_I == 1'b1)begin CLOCK_Start <= 1'b1 ; end CLK_VMAX1 <= SW_VMAX_I ; CLK_VMAX2 <= CLK_VMAX1 ; if(CLK_VMAX2 == 1'b0 & CLK_VMAX1 == 1'b1)begin Pulse_1Sec <= 1'b0 ; Sec1_counter <=32'b0 ; end else begin if (CLK_VMAX2 == 1'b1 )begin //SW_VMAX_I ¤¬¤ª¤µ¤ì¤¿¤é¥Ö¡¼¥¹¥È¥â¡¼¥É if(Sec1_counter == param_VMAXsec)begin Pulse_1Sec <= 1'b1 ; Sec1_counter <= 32'b0 ; end else begin Pulse_1Sec <= 1'b0 ; Sec1_counter <= Sec1_counter + 1 ; end end else begin if(Sec1_counter == param_1Second)begin Pulse_1Sec <= 1'b1 ; Sec1_counter <= 32'b0 ; end else begin Pulse_1Sec <= 1'b0 ; Sec1_counter <= Sec1_counter + 1 ; end end end if(Pulse_1Sec == 1'b1)begin SEC_Prompt <= !SEC_Prompt ; end end end //Éäΰ̥«¥¦¥ó¥¿ always@(posedge CLK_I or posedge SW_RESET_I) begin if(SW_RESET_I == 1'b1)begin Count_1sec <= 0 ; Count_10sec <= 0 ; end else begin if(CLOCK_Start == 1'b1 & Pulse_1Sec == 1'b1)begin //1¤Î°Ì¤Î¥Á¥§¥Ã¥¯ if(Cnt_1sec_is_9 == 1'b1)begin//²¼assignʸ¤è¤êC nt_1sec_is9 ¤Î½é´üÃͤÏ0 Count_1sec <= 0 ; end else begin Count_1sec <= Count_1sec + 1 ;//0->9¤ò·«¤êÊÖ¤¹ end //10¤Î°Ì¤Î¥Á¥§¥Ã¥¯ if(Cnt_sec_is_59 == 1'b1)begin Count_10sec <= 0 ; end else begin if(Cnt_1sec_is_9 ==1'b1) begin //Cnt_1sec_is_9¤¬9¤Î¤È¤ Count_10sec <= Count_10sec + 1 ; //0->59¤ò·«¤êÊÖ¤¹ end end end end end assign #1 Cnt_1sec_is_9 = (Count_1sec == 4'd9)?1'b1:1'b0 ; assign #1 Cnt_sec_is_59 = (Count_10sec == 3'd5&Count_1sec == 4'd9)?1'b1:1'b0 ; //ʬ¤Î°Ì¥«¥¦¥ó¥¿ always@(posedge CLK_I or posedge SW_RESET_I) begin if(SW_RESET_I == 1'b1)begin Count_1min <= 0 ; Count_10min <= 0 ; end else begin if(CLOCK_Start == 1'b1 & Pulse_1Sec == 1'b1)begin if(Cnt_sec_is_59 ==1'b1)begin //59Éäˤʤ俤é //1¤Î°Ì¤Î¥Á¥§¥Ã¥¯ if(Cnt_1min_is_9 == 1'b1)begin//²¼assignʸ¤è¤êCnt_1min_is9 ¤Î½é´üÃͤÏ0 Count_1min <= 0 ; end else begin Count_1min <= Count_1min + 1 ;//0->9¤ò·«¤êÊÖ¤¹ end //10¤Î°Ì¤Î¥Á¥§¥Ã¥¯ if(Cnt_min_is_59 == 1'b1)begin Count_10min <= 0 ; end else begin if(Cnt_1min_is_9 ==1'b1)begin //Cnt_1sec_is_9¤¬9¤Î¤È¤ Count_10min <= Count_10min + 1 ; //0->59¤ò·«¤êÊÖ¤¹ end end end end end end assign Cnt_1min_is_9 = (Count_1min == 4'd9 )?1'b1 :1'b0 ; assign Cnt_min_is_59 = (Count_10min == 3'd5 & Count_1min == 4'd9 )?1'b1 :1'b0 ; //»þ¤Î°Ì¥«¥¦¥ó¥¿always@(posedge CLK_I or posedge SW_RESET_I) always@(posedge CLK_I or posedge SW_RESET_I) begin if(SW_RESET_I == 1'b1)begin Count_1hour <= 0 ; Count_10hour <= 0 ; end else begin if(CLOCK_Start == 1'b1 & Pulse_1Sec == 1'b1)begin if(Cnt_sec_is_59 ==1'b1 & Cnt_min_is_59 ==1'b1)begin //59ʬ59Éäˤʤ俤é //1¤Î°Ì¤Î¥Á¥§¥Ã¥¯ if(Cnt_1hour_is_9 == 1'b1 | Cnt_hour_is_11 == 1'b1 )begin//9»þ¤«11»þ¤Ë¤Ê¤Ã¤¿¤é Count_1hour <= 0 ; end else begin Count_1hour <= Count_1hour + 1 ;//0->9¤ò·«¤êÊÖ¤¹ end //10¤Î°Ì¤Î¥Á¥§¥Ã¥¯ if(Cnt_hour_is_11 == 1'b1)begin Count_10hour <= 0 ; end else begin if(Cnt_1hour_is_9 ==1'b1)begin Count_10hour <= Count_10hour + 1 ; end end end end end end assign Cnt_1hour_is_9 = (Count_1hour == 4'd9 )?1'b1 :1'b0 ; assign Cnt_hour_is_11 = (Count_10hour == 1'd1 & Count_1hour == 4'd1 )?1'b1 :1'b0 ; //7¥»¥°¥á¥ó¥ÈLEDɽ¼¨Éô assign TIM_4 = (SW_DispSEC_I == 1'b0 )?{3'b0,Count_10hour}:{1'b0,Count_10min};//SW_DipsSEC_I¤Çɽ¼¨¤ò"»þʬ","ʬÉÃ"ÀÚ¤êÂؤ¨ assign TIM_3 = (SW_DispSEC_I == 1'b0 )?{ Count_1hour}:{ Count_1min}; assign TIM_2 = (SW_DispSEC_I == 1'b0 )?{1'b0,Count_10min}:{ 1'b0,Count_10sec}; assign TIM_1 = (SW_DispSEC_I == 1'b0 )?{ Count_1min}:{ Count_1sec}; always@(posedge CLK_I) begin case(TIM_4) 4'b0000 : node_SEG4 <= 8'b00111111 ; //'0' display 4'b0001 : node_SEG4 <= 8'b00000110 ; //'1' display 4'b0010 : node_SEG4 <= 8'b01011011 ; //'2' display 4'b0011 : node_SEG4 <= 8'b01001111 ; //'3' display 4'b0100 : node_SEG4 <= 8'b01100110 ; //'4' display 4'b0101 : node_SEG4 <= 8'b01101101 ; //'5' display 4'b0110 : node_SEG4 <= 8'b01111101 ; //'6' display 4'b0111 : node_SEG4 <= 8'b00100111 ; //'7' display 4'b1000 : node_SEG4 <= 8'b01111111 ; //'8' display 4'b1001 : node_SEG4 <= 8'b01101111 ; //'9' display default : node_SEG4 <= 8'b01000000 ; //'-' display endcase case(TIM_3) 4'b0000 : node_SEG3 <= 8'b00111111 ; //'0' display 4'b0001 : node_SEG3 <= 8'b00000110 ; //'1' display 4'b0010 : node_SEG3 <= 8'b01011011 ; //'2' display 4'b0011 : node_SEG3 <= 8'b01001111 ; //'3' display 4'b0100 : node_SEG3 <= 8'b01100110 ; //'4' display 4'b0101 : node_SEG3 <= 8'b01101101 ; //'5' display 4'b0110 : node_SEG3 <= 8'b01111101 ; //'6' display 4'b0111 : node_SEG3 <= 8'b00100111 ; //'7' display 4'b1000 : node_SEG3 <= 8'b01111111 ; //'8' display 4'b1001 : node_SEG3 <= 8'b01101111 ; //'9' display default : node_SEG3 <= 8'b01000000 ; //'-' display endcase case(TIM_2) 4'b0000 : node_SEG2 <= 8'b00111111 ; //'0' display 4'b0001 : node_SEG2 <= 8'b00000110 ; //'1' display 4'b0010 : node_SEG2 <= 8'b01011011 ; //'2' display 4'b0011 : node_SEG2 <= 8'b01001111 ; //'3' display 4'b0100 : node_SEG2 <= 8'b01100110 ; //'4' display 4'b0101 : node_SEG2 <= 8'b01101101 ; //'5' display 4'b0110 : node_SEG2 <= 8'b01111101 ; //'6' display 4'b0111 : node_SEG2 <= 8'b00100111 ; //'7' display 4'b1000 : node_SEG2 <= 8'b01111111 ; //'8' display 4'b1001 : node_SEG2 <= 8'b01101111 ; //'9' display default : node_SEG2 <= 8'b01000000 ; //'-' display endcase case(TIM_1) 4'b0000 : node_SEG1 <= 8'b00111111 ; //'0' display 4'b0001 : node_SEG1 <= 8'b00000110 ; //'1' display 4'b0010 : node_SEG1 <= 8'b01011011 ; //'2' display 4'b0011 : node_SEG1 <= 8'b01001111 ; //'3' display 4'b0100 : node_SEG1 <= 8'b01100110 ; //'4' display 4'b0101 : node_SEG1 <= 8'b01101101 ; //'5' display 4'b0110 : node_SEG1 <= 8'b01111101 ; //'6' display 4'b0111 : node_SEG1 <= 8'b00100111 ; //'7' display 4'b1000 : node_SEG1 <= 8'b01111111 ; //'8' display 4'b1001 : node_SEG1 <= 8'b01101111 ; //'9' display default : node_SEG1 <= 8'b01000000 ; //'-' display endcase end //¥À¥¤¥Ê¥ß¥Ã¥¯ÅÀÅôÊý¼°ÍѤηå»ØÄêÆâÉô¥Î¡¼¥É²óÏ©Éô always@(posedge CLK_I) begin OEN_counter <= OEN_counter + 1 ; end // assign OE_DIGIT = OEN_counter[19:18] ; assign OE_DIGIT = OEN_counter[17:16] ;
//OE_DIGIT¤ÎÃͤǡ¢½ÐÎÏÃͤò»þʬ³ä¤ÇSEG_O¤Ë°ú¤ÅϤ¹ always@(posedge CLK_I) begin case(OE_DIGIT) 2'b11: SEG_O <= ‾node_SEG4 ;//node_SEG1(1¤Î°Ì)¤ÎÏÀÍýȿž¤ÇSEG_O¤Ë³ä¤êÅö¤Æ 2'b10: SEG_O <= ‾node_SEG3 ; 2'b01: SEG_O <= ‾node_SEG2 ; 2'b00: SEG_O <= ‾node_SEG1 ; endcase end //ÅÀÅô¤¹¤ë7¥»¥°É½¼¨Éô(ÉôÉÊ)¤òÁªÂò¤¹¤ë always@(posedge CLK_I) begin case(OE_DIGIT) 2'b00: SEGEN_O <= 4'b0001 ;//1·å¤Îɽ¼¨¥Ç¡¼¥¿¤ò1·å¤Îɽ¼¨Éô¤Øɽ¼¨µö²Ä¤¹¤ë 2'b01: SEGEN_O <= 4'b0010 ; 2'b10: SEGEN_O <= 4'b0100 ; default : SEGEN_O <= 4'b1000;//¥Ç¥Õ¥©¥ë¥È¤Ï1000·åÌÜ͸ú endcase end //ÅÀÅô¤¹¤ë7¥»¥°É½¼¨Éô¤ò»ØÄꤹ¤ë½ÐÎÏ¥Ô¥ó¤Ø½ÐÎÏ»ØÄê¤ò³ä¤êÅö¤Æ¤ë assign DP1OEN_O = !SEGEN_O[1] ;//SEGEN_O¤Î²¼°Ì1bit¤¬1(1·åÌܤÎɽ¼¨Éô¤ò͸ú¤È¤·¤¿¤¤¤È¤)¤ò½ÐÎÏ¥Ô¥ó¤ËÈ¿±Ç¤¹¤ë assign DP2OEN_O = !SEGEN_O[2] ; assign DP3OEN_O = !SEGEN_O[3] ; assign DP4OEN_O = !SEGEN_O[4] ; //LEDɽ¼¨¡¡¥Ç¥Ð¥Ã¥°ÍÑ assign LED1_O = SEC_Prompt ; assign LED2_O = 1'b1 ; assign LED3_O = 1'b1 ; assign LED4_O = 1'b1 ; endmodule
¡¦2-8 TIMER180sec.constrainfile
#¡¡¥¯¥í¥Ã¥¯¿®¹æ NET "CLK_I" LOC = "P63" ; #¡¡LED½ÐÎÏ NET "LED1_O" LOC = "P17" ; NET "LED2_O" LOC = "P18" ; NET "LED3_O" LOC = "P22" ; NET "LED4_O" LOC = "P23" ;
# ¥¹¥¤¥Ã¥ÁÆþÎÏ NET "SW_RESET_I" LOC = "P30" ; NET "SW_START_I" LOC = "P27" ; NET "SW_DispSEC_I" LOC = "P26" ; NET "SW_VMAX_I" LOC = "P24" ; # 7¥»¥°¥á¥ó¥ÈLED¡¦ÅÀÅô͸ú¥é¥¤¥ó NET "DP1OEN_O" LOC = "P86"; NET "DP2OEN_O" LOC = "P85"; NET "DP3OEN_O" LOC = "P3"; NET "DP4OEN_O" LOC = "P2"; # 7¥»¥°¥á¥ó¥ÈLED¡¦³Æ¥¨¥ì¥á¥ó¥ÈLED NET "SEG_O<1>" LOC = "P94"; NET "SEG_O<2>" LOC = "P92"; NET "SEG_O<3>" LOC = "P98"; NET "SEG_O<4>" LOC = "P71"; NET "SEG_O<5>" LOC = "P70"; NET "SEG_O<6>" LOC = "P90"; NET "SEG_O<7>" LOC = "P91"; NET "SEG_O<8>" LOC = "P95"; #¡¡¥æ¡¼¥¶µ¡Ç½³ÈÄ¥¥³¥Í¥¯¥¿¡¦ÆþÎÏÀìÍѥ饤¥ó #NET "GPIN" LOC = "P38" ; #¡¡¥æ¡¼¥¶µ¡Ç½³ÈÄ¥¥³¥Í¥¯¥¿¡¦Æþ½ÐÎϥ饤¥ó #NET "GPIO<1>" LOC = "P32" ; #NET "GPIO<2>" LOC = "P33" ; #NET "GPIO<3>" LOC = "P35" ; #NET "GPIO<4>" LOC = "P36" ; #NET "GPIO<5>" LOC = "P40" ; #NET "GPIO<6>" LOC = "P41" ; #NET "GPIO<7>" LOC = "P47" ; #NET "GPIO<8>" LOC = "P48" ; #NET "GPIO<9>" LOC = "P49" ; #NET "GPIO<10>" LOC = "P53" ; #NET "GPIO<11>" LOC = "P54" ; #NET "GPIO<12>" LOC = "P57" ; #NET "GPIO<13>" LOC = "P58" ; #NET "GPIO<14>" LOC = "P60" ; #NET "GPIO<15>" LOC = "P61" ; #¡¡RS-232C¥·¥ê¥¢¥ë¥Ý¡¼¥È #NET "TxD" LOC = "P83" ; #NET "RxD" LOC = "P79" ; #
module postcodedisplay(//¥â¥¸¥å¡¼¥ëÀë¸À³«»Ï OSCCLK_in, //¥Ý¡¼¥ÈÄêµÁ RESETDRV_in, ISA_SA_in, ISA_SD_in, nISA_AEN_in, nISA_IOW_in, nSEG7LED_out, nSEG7LEDCOM_out, nRESET_out ); //******Æþ½ÐÎÏ******// input OSCCLK_in; input RESETDRV_in; input[11:0] ISA_SA_in; inout[7:0] ISA_SD_in; inout nISA_AEN_in; inout nISA_IOW_in; output[6:0] nSEG7LED_out; output[1:0] nSEG7LEDCOM_out; output nRESET_out; //******ÆâÉô¥Î¡¼¥É******// parameter F14318180=24'h6D3D32; parameter PCODEADD=12'h80; reg[7:0] reg_ISA_SD; reg[7:0] nod_SEG7LEDBCD; reg[6:0] nod_SEG7LED_0; reg[6:0] nod_SEG7LED_1; reg reg_INTCLK; reg[23:0] reg_INTCLKCNT; reg reg_SCANPLACE; //******ÆâÉô²óÏ©******// /**********************/ /*¥«¥¦¥ó¥¿Éô */ /**********************/ always@(posedge OSCCLK) begin if(reg_INTCLKCNT == F14318180 ) begin //¤â¤·7159090²ó¿ô¤¨¤¿¤é¥«¥¦¥ó¥¿¤ò¥ê¥»¥Ã¥È¤¹¤ë reg_INTCLKCNT <= 24'h000000 ; reg_SCANPLACE <= 1'b1; end else begin reg_INTCLKCNT <= reg_INTCLKCNT + 1 ; reg_SCANPLACE <= 1'b0 ; end end /**********************/ /*¥¯¥í¥Ã¥¯À¸À®¡¡ */ /**********************/ always@(posedge OSCCLK) begin if(reg_INTCLK == 1'b1 )begin reg_INTCLK <= !reg_INTCLK ; end end /**********************/ /*IO¥¢¥É¥ì¥¹¥é¥Ã¥Á */ /**********************/ always@(posedge nISA_IOW_in) begin if(nISA_IOW_in == 1'b1)then if(nISA_AEN_in == 1'b1 and ISA_SA_in == PCODEADD)begin reg_ISA_SD <= ISA_SD_in; end end
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1 | ||||||||||
DCDC | MCP1826S-1802E/DB | MCP1700T-1802E/TT | LTC3670 | R1130 | TLV7* | TPS7A2018PDBVR | BU18SD5WG-TL | ADP7118AUJZ-1.8-R7 | LDS3985 | MC33375ST-1.8T3G |
¼ÂÀÓ | 5M570ZT144C5N | MAX V CPLD Development Kit Board | ||||||||
¥á¡¼¥«¡¼ | microchip | microchip | AnalogDevices? | RICOH | TI | TI | ROHM | AnalogDevices? | ST-micro | OnSemi? |
DropDown? | Typ0.25V | Typ0.15V,Max0.35V | Max0.3V | Max1.5V | ||||||
Package | SOT23-3 | SOT23-3 | DDB | |||||||
InputVoltage? | 2.3¡Á6V | 2.3¡Á6V | 2.5¡Á5.5V | 2.5¡Á8V | 1.7¡Á6.8V | 2.5¡Á6V | ||||
OutputVoltage? | 1.8V | 1.8V | 1.8V | 1.8V | 1.8V | |||||
Iout | 1A | 0.2A | 0.15A(max0.25A) | 0.5A | ||||||
»¼º | 540mW | |||||||||
ÀºÅÙ | 2% | 3% | 2.50% | 2% | ||||||
Tj | -40¡Á125¡î | -40¡Á125¡î | -40¡Á85¡î | -40¡Á105¡î | ||||||
Tj125¡î | ||||||||||
Vin | 3.3 | 3.3 | 3.3 | 3.3 | ||||||
Vin max | 3.465 | 3.465 | 3.465 | 3.465 | ||||||
Vout | 1.8 | 1.8 | 1.8 | 1.8 | ||||||
Vout min | 1.71 | 1.71 | 1.71 | 1.71 | ||||||
ùV | 1.755 | 1.755 | 1.755 | 1.755 | ||||||
Iout | 0.5 | 0.2 | 0.2 | 0.2 | ||||||
»¼º | 0.8775 | 0.351 | 0.351 | 0.351 | ||||||
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