電気電子設計 / Ordering_infomation

電気電子設計

・DAC_SPI2_24 †

目的：DAC ICのSPI制御用マニュアル入力装置を作成する。24bit以下のシリアル送信に対応する。bit数はDIPSWにて可変とする。

・ハードウェアセットアップ †

(1)構成概略
下記のような構成を考える。

#ref(): File not found: "max5spi_24_.png" at page "電気電子設計/Ordering_infomation"

入力デバイスはタクトSWとし、これにて24bitデータを入力し、FPGAでSPI制御する
(2)仕様

(3)ハードウェア構成

#ref(): File not found: "max5spi_24_1.png" at page "電気電子設計/Ordering_infomation"

・ピンアサイン

・RTL記述内容ソース †

 module DAC_SPI2_24l2(
SW1, //input LSB
SW2,
SW3,
SW4, //input MSB
SW5,//set out
SW6,  //20
SW7, //24
DSW,
DSOUT,
CLK, //standard clock
SCK, //serial clock
NSCK,
NCS,
RST,
SEVEN_SEG_DATA[7:0],
SEL[6:1],///[4:1]
SOUT,
CS_COUNTER[4:0],

//1/25 added
NLDAC
	);
	
	input CLK;
	input RST;
	input SW1;
	input SW2;
	input SW3;
	input SW4;
	input SW5;
	input SW6;
	input SW7;
	input [7:0] DSW;
	output [7:0] DSOUT;
	output SCK;
	output NSCK;
	output NCS;
  output reg[7:0] SEVEN_SEG_DATA;
	output [6:1] SEL;  // [4:1]
	output SOUT;
	output [4:0]CS_COUNTER;
	output NLDAC;
	reg sw1;
	reg sw2;
	reg sw3;
	reg sw4;
	reg sw5;
	reg sw5out;
	reg sw6;
	reg sw7;
	//reg [15:0] sout;
	reg [23:0] sout;
	reg[15:0] sw1_counter;
	reg[15:0] sw2_counter;
	reg[15:0] sw3_counter;
	reg[15:0] sw4_counter;
	reg[4:0] sw5_counter;
	reg[15:0] sw6_counter;
	reg[15:0] sw7_counter;
	reg[31:0] sec_cnt; //slow clock generation
	reg sec1_flag; //slow clock generation
	reg toggle_flag; //slow clock generation
	reg[2:0] enable_seg;//[1:]
	reg[6:1] sel;//4:1
	reg[3:0] seven_seg1_counter;
	reg[3:0] seven_seg2_counter;
	reg[3:0] seven_seg3_counter;
	reg[3:0] seven_seg4_counter;
	reg[3:0] seven_seg5_counter;
	reg[3:0] seven_seg6_counter;
	reg[7:0] seven_seg1_hold;
	reg[7:0] seven_seg2_hold;
	reg[7:0] seven_seg3_hold;
	reg[7:0] seven_seg4_hold;
	reg[7:0] seven_seg5_hold;
	reg[7:0] seven_seg6_hold;
	reg[7:0] seven_seg;
	reg sck;
	reg ncs;
	reg nsck;
	reg[4:0]cs_counter;
	reg cs_count_full;	
	reg [7:0]bitlength;
	reg nldac;
	reg[4:0]l_counter;
	reg lflag;
	reg lflag2;
	reg lflag3;
	
	initial ncs <= 1'b1 ;
	//parameter   F14M7456_cnt=32'h00708000 ;//0.5sec interval
	//parameter   F14M7456_cnt=32'h00168000 ;//0.1sec interval
	//  parameter   F14M7456_cnt=32'h0039999 ;//0.016sec interval inputting clk: at 14.756Mhz
	//parameter   F14M7456_cnt=32'h0024000 ;//0.01sec interval 
	//parameter   F14M7456_cnt=32'h00003999 ; //0.001sec interval
	parameter   F14M7456_cnt=32'h00000040 ; //115.2kbps interval
	//  parameter   F14M7456_cnt=32'h00000002 ; //3.68MHz 268nsec
  // parameter   F14M7456_cnt=32'h000005C2 ; //0.0001sec interval
	//parameter   F14M7456_cnt=32'h0000002E1 ; //0.000005sec interval 10kHz
	
  parameter	selinit_value = 6'b100000	;
	initial	cs_counter = 5'b00000;
	
	initial sw1_counter = 16'h0000;
	initial sw2_counter = 16'h0000;
	initial sw3_counter = 16'h0000;
	initial sw4_counter = 16'h0000;
	initial sw5_counter = 16'h0000;
	initial sw6_counter = 16'h0000;
	initial sw7_counter = 16'h0000;
 initial seven_seg1_hold =8'b00000110;
 initial seven_seg2_hold =8'b01011011;
 initial seven_seg3_hold =8'b01001111;
 initial seven_seg4_hold =8'b01100110;
 initial seven_seg5_hold =8'b01101101;
 initial seven_seg6_hold =8'b01111101;
	
	initial cs_count_full =1'b0;
	initial sout = 24'b0000;//16
	initial nldac =1'b1;
	initial l_counter=5'b00000;
	
always@(posedge CLK)
begin
bitlength <= ~DSW;
end

always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw1_counter <= 16'b0000000000000000; //16bit 65535times(aprroximately 6.5msec sampling) 
end else begin
sw1_counter <= sw1_counter +1'b1;
end
end

always@(posedge CLK)
begin
if(sw1_counter ==0)begin
sw1 <= SW1;
end
end

always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw2_counter <= 16'b0000000000000000;
end else begin
sw2_counter <= sw2_counter +1'b1;
end
end

always@(posedge CLK)
begin
if(sw2_counter ==0)begin
sw2 <= SW2;
end
end

always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw3_counter <= 16'b0000000000000000;
end else begin
sw3_counter <= sw3_counter +1'b1;
end
end

always@(posedge CLK)
begin
if(sw3_counter ==0)begin
sw3 <= SW3;
end
end

always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw4_counter <= 16'b0000000000000000;
end else begin
sw4_counter <= sw4_counter +1'b1;
end
end

always@(posedge CLK)
begin
if(sw4_counter ==0)begin
sw4 <= SW4;
end
end

always@(posedge NSCK or negedge RST)
begin
if(RST ==1'b0)begin
sw5_counter <= 5'b00000;
end else begin
sw5_counter <= sw5_counter +1'b1;
end
end

//always@(posedge CLK)
always@(posedge NSCK)
begin
if(sw5_counter ==0)begin
sw5 <= SW5;
end
end

always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw6_counter <= 16'b0000000000000000;
end else begin
sw6_counter <= sw6_counter +1'b1;
end
end

always@(posedge CLK)
begin
if(sw6_counter ==0)begin
sw6 <= SW6;
end
end

always@(posedge CLK or negedge RST)
begin
if(RST ==1'b0)begin
sw7_counter <= 16'b0000000000000000;
end else begin
sw7_counter <= sw7_counter +1'b1;
end
end

always@(posedge CLK)
begin
if(sw7_counter ==0)begin
sw7 <= SW7;
end
end

assign DSOUT =DSW;

//***The end of chattring rejection***//

always@(posedge CLK)
begin
 if(sec_cnt == F14M7456_cnt) begin
	  sec_cnt <= 32'h00000000 ; //counter counting up to the parameter(refer to No 52th row)
	  sec1_flag <= 1'b1; 
	end else begin
	  sec_cnt <= sec_cnt + 1 ;
	  sec1_flag <= 1'b0 ;
	end
end

always@(posedge CLK)
begin
  if(sec1_flag == 1'b1 )begin
	 toggle_flag <= !toggle_flag ;
	end
end

//assign SCK =!toggle_flag ;
assign SCK =!toggle_flag ;//&& ~sw5out;
assign NSCK =toggle_flag;

always@(negedge sw1 or negedge sw2 or negedge sw3 or negedge sw4 or negedge sw6 or negedge sw7 or negedge RST or posedge CLK)
begin if(RST ==1'b0)begin
seven_seg1_hold <=8'b00000110;
seven_seg2_hold <=8'b01011011;
seven_seg3_hold <=8'b01001111;
seven_seg4_hold <=8'b01100110;
seven_seg5_hold <=8'b01101101;
seven_seg6_hold <=8'b01111101;
end else begin
 	case(seven_seg1_counter)
	4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0'
	4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c'
	4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F'
	default: seven_seg1_hold <= 8'b00000110;
	endcase
	
 	case(seven_seg2_counter)
	4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0
	4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c'
	4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F'
	 default: seven_seg2_hold <= 8'b01011011;
	endcase
	case(seven_seg3_counter)
	4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0'
	4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c'
	4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F'
  default: seven_seg3_hold <= 8'b01001111;
	endcase
	case(seven_seg4_counter)
	4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0'
	4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c'
	4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F'
	default: seven_seg4_hold <= 8'b01100110;
	endcase
	case(seven_seg5_counter)
	4'b0000 : seven_seg5_hold<= 8'b00111111 ; //'0'
	4'b0001 : seven_seg5_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg5_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg5_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg5_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg5_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg5_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg5_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg5_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg5_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg5_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg5_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg5_hold <= 8'b01011000 ; //'c'
	4'b1101 : seven_seg5_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg5_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg5_hold <= 8'b01110001 ; //'F'
	default: seven_seg5_hold <= 8'b01101101;
	endcase
	case(seven_seg6_counter)
	4'b0000 : seven_seg6_hold<= 8'b00111111 ; //'0'
	4'b0001 : seven_seg6_hold <= 8'b00000110 ; //'1'
	4'b0010 :seven_seg6_hold<= 8'b01011011 ; //'2'
	4'b0011 : seven_seg6_hold <= 8'b01001111 ; //'3'
	4'b0100 : seven_seg6_hold <= 8'b01100110 ; //'4'
	4'b0101 : seven_seg6_hold <= 8'b01101101 ; //'5'
	4'b0110 : seven_seg6_hold <= 8'b01111101 ; //'6'
	4'b0111 : seven_seg6_hold <= 8'b00100111 ; //'7'
	4'b1000 : seven_seg6_hold <= 8'b01111111 ; //'8'
	4'b1001 : seven_seg6_hold <= 8'b01101111 ; //'9'
	4'b1010 : seven_seg6_hold <= 8'b01110111 ; //'A'
	4'b1011 : seven_seg6_hold <= 8'b01111100 ; //'b'
	4'b1100 : seven_seg6_hold <= 8'b01011000 ; //'c'
	4'b1101 : seven_seg6_hold <= 8'b01011110 ; //'d'
	4'b1110 : seven_seg6_hold <= 8'b01111001 ; //'E'
	4'b1111 : seven_seg6_hold <= 8'b01110001 ; //'F'
	default: seven_seg6_hold <= 8'b01111101;
	endcase
end
end
	
always@(posedge SCK or  negedge RST)begin
 if(RST == 1'b0 )begin
	  enable_seg <= 3'b000;
	end else if(enable_seg == 3'b101)begin
	  enable_seg <=3'b000;
 end else begin
  enable_seg <= enable_seg +1'b1;
	end
end

always@(posedge SCK or  negedge RST)begin
 if(RST == 1'b0 )begin
	  sel <= selinit_value;
	  end else begin
sel[2] <= sel[1]	;	//シフト動作を開始する
sel[3] <= sel[2]	;	//シフト動作を開始する
sel[4] <= sel[3]	;	//シフト動作を開始する
sel[5] <= sel[4]	;
sel[6] <= sel[5]	;
sel[1] <= sel[6]	;
  end
end

assign SEL[6:1] = ~sel[6:1];  //[4:1]

always@( negedge RST or posedge sw1 )begin
  if( RST == 1'b0 )begin
    seven_seg1_counter <= 4'b0000;
  end  else begin
		seven_seg1_counter <= seven_seg1_counter  + 1'b1;
end
end

always@( negedge RST or negedge sw2)begin
  if( RST == 1'b0)begin
    seven_seg2_counter <= 4'b0000;
  end  else begin
		seven_seg2_counter <= seven_seg2_counter  + 1'b1;
    end
end
 
always@( negedge RST or negedge sw3)begin
  if( RST == 1'b0)begin
    seven_seg3_counter <= 4'b0000;
  end  else begin
		seven_seg3_counter <= seven_seg3_counter  + 1'b1;
    end
end

always@( negedge RST or negedge sw4)begin
  if( RST == 1'b0)begin
    seven_seg4_counter <= 4'b0000;
  end  else begin
		seven_seg4_counter <= seven_seg4_counter  + 1'b1;
    end
end

always@( negedge RST or negedge sw6)begin
  if( RST == 1'b0)begin
    seven_seg5_counter <= 4'b0000;
  end  else begin
		seven_seg5_counter <= seven_seg5_counter  + 1'b1;
    end
end

always@( negedge RST or negedge sw7)begin
  if( RST == 1'b0)begin
    seven_seg6_counter <= 4'b0000;
  end  else begin
		seven_seg6_counter <= seven_seg6_counter  + 1'b1;
    end
end

always@* //* whenever inputs change,  holding counter value as the resister "SEVEN_SEG_DATA"
begin
case(enable_seg)
	3'b000:  SEVEN_SEG_DATA <= ~seven_seg6_hold;
	3'b001:  SEVEN_SEG_DATA<=~seven_seg1_hold;
 3'b010:  SEVEN_SEG_DATA<=~seven_seg2_hold;
 3'b011:  SEVEN_SEG_DATA<=~seven_seg3_hold;
	 3'b100:  SEVEN_SEG_DATA<=~seven_seg4_hold;
	  3'b101:  SEVEN_SEG_DATA<=~seven_seg5_hold;
		endcase
	end
	  	
always@(negedge RST or negedge sw5 or posedge cs_count_full )// )//posedge cs_counter )
	 begin
  if( RST == 1'b0)begin
   sw5out <= 1'b1;
		 end else if(cs_count_full ==1'b1)begin //[4]
		//  end else if(cs_count_full ==1'b1 && NSCK == 1'b0)begin //[4]
		sw5out <= 1'b1;
		end else begin
		sw5out <=1'b0;
end
end
 
assign NCS = sw5out;

always@(posedge NSCK or  negedge RST )//SCK
begin
 if(RST == 1'b0 )begin
	   cs_counter<= 5'b00000;
		cs_count_full<=1'b0;
//		sw5out<=1'b1;
//end else if(cs_counter ==5'b11000)begin
end else if(cs_counter == bitlength)begin
		cs_counter <=5'b00000;
		cs_count_full<=1'b0;
//     sw5out<=1'b1;
// end else if(cs_counter == 5'b10001)begin
//  cs_counter <=5'b00000;
//	sw5out <=1'b0;
//end else if(cs_counter ==5'b10111)begin
  end else if(cs_counter ==bitlength-1)begin
cs_count_full<=1'b1;
cs_counter <= cs_counter +1'b1;
end else if(sw5out ==1'b0)
	begin
  cs_counter <= cs_counter +1'b1;
	 cs_count_full<=1'b0;

	end else begin
	cs_counter <=5'b00000;
	cs_count_full<=1'b0;

//	sw5out <=1'b0;
	end
end

always@(posedge NSCK)
begin
lflag <= cs_count_full;
lflag2 <= lflag ;
lflag3 <= lflag2;
nldac <= lflag3;
end 

assign NLDAC = ~nldac;




//assign  CS_COUNTER = cs_counter ;
assign  CS_COUNTER = l_counter ;
/*
always@(posedge NSCK or  negedge RST )
	begin
 if(RST == 1'b0 )begin
	   sout<=16'b0000000000000000;
	end else if(sw5out ==1'b0)
	begin
	sout <= {sout[14:0],sout[15] };
	end else begin
	sout <={seven_seg4_counter,seven_seg3_counter,seven_seg2_counter,seven_seg1_counter};
	end
end

//assign SOUT = (sw5out==0)? sout[15]:1'b0;
assign SOUT = sout[15];
*/
 
always@(posedge NSCK or  negedge RST )
	begin
 if(RST == 1'b0 )begin
	   sout<=24'b000000000000000000000000;
	end else if(sw5out ==1'b0)
	begin
	sout <= {sout[22:0],sout[23] };
	end else begin
	sout <={seven_seg6_counter,seven_seg5_counter,seven_seg4_counter,seven_seg3_counter,seven_seg2_counter,seven_seg1_counter};
	end
end

//assign SOUT = (sw5out==0)? sout[15]:1'b0;
assign SOUT = sout[23];

endmodule 

結果 †

下表に、実際に出力させてみたときの電圧値を示す。~
#ref(result1.png,left,nowrap,添付ファイルの画像)~