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1.PORT80h DECODER
1-1.タイミングチャート
1-2-1.ピン一覧_評価ボードAZMMAXVT1
1-2-2.ピン一覧_CPLD_5M570ZT144C5N
1-3.ソースコード
1-4.テストベンチソースコード
下記のような構成を考える。
#ref(): File not found: "lpc1.png" at page "verilog/PORT80h translator1_570"
CN1 | 240 | 570 | CN2 | 240 | 570 | |||||||||||
Pin | 番号 | 種別 | 種別 | CPLD | 信号名 | 基板上LED | In/Out | Pin | 番号 | 説明 | Pin | 信号名 | 基板上LED | In/Out | ||
1 | VCC_A | - | +3.3V | +3.3V | - | 1 | VCC_B | - | +3.3V | +3.3V | - | |||||
2 | VCC_A | - | +3.3V | +3.3V | - | 2 | VCC_B | - | +3.3V | +3.3V | - | |||||
3 | GND | - | GND | - | 3 | GND | - | GND | - | |||||||
4 | GND | - | GND | - | 4 | GND | - | GND | - | |||||||
5 | I/O | 2 | 16 | 汎用IO | 5 | I/O | 91 | 133 | 汎用IO | 7LED1_A | Out | |||||
6 | I | 14 | 20 | 入力専用端子 | RST | In | 6 | I/O | 90 | 132 | 汎用IO | 7LED2_B | Out | |||
7 | I/O | 3 | 21 | 汎用IO | POSTDATA[7] | LED7 | Out | 7 | I/O | 89 | 129 | 汎用IO | 7LED3_C | Out | ||
8 | I/O | 4 | 22 | 汎用IO | POSTDATA[6] | LED6 | Out | 8 | I/O | 88 | 127 | 汎用IO | 7LED4_D | Out | ||
9 | I/O | 5 | 23 | 汎用IO | POSTDATA[5] | LED5 | Out | 9 | I/O | 87 | 125 | 汎用IO | 7LED5_E | Out | ||
10 | I/O | 6 | 24 | 汎用IO | POSTDATA[4] | LED4 | Out | 10 | I/O | 86 | 122 | 汎用IO | 7LED6_F | Out | ||
11 | I/O | 7 | 27 | 汎用IO | POSTDATA[3] | LED3 | Out | 11 | I/O | 85 | 121 | 汎用IO | 7LED7_G | Out | ||
12 | I/O | 8 | 28 | 汎用IO | POSTDATA[2] | LED2 | Out | 12 | I/O | 84 | 120 | 汎用IO | 7LED8_dot | Out | ||
13 | I/O | 15 | 29 | 汎用IO | POSTDATA[1] | LED1 | Out | 13 | I/O | 83 | 119 | 汎用IO | LADCOM[3] | In | ||
14 | I/O | 16 | 30 | 汎用IO | POSTDATA[0] | LED0 | Out | 14 | I/O | 82 | 118 | 汎用IO | LADCOM[2] | In | ||
15 | I/O | 17 | 31 | 汎用IO | tx | Out | 15 | I/O | 81 | 113 | 汎用IO | LADCOM[1] | In | |||
16 | I/O | 18 | 32 | 汎用IO | rx | In | 16 | I/O | 78 | 112 | 汎用IO | LADCOM[0] | In | |||
17 | I/O | 19 | 37 | 汎用IO | 17 | I/O | 77 | 111 | 汎用IO | DSEL1 | Out | |||||
18 | I/O | 20 | 38 | 汎用IO | 18 | I/O | 76 | 110 | 汎用IO | DSEL2 | Out | |||||
19 | GND | - | 19 | GND | - | |||||||||||
20 | GND | - | 20 | GND | - | |||||||||||
21 | GND | - | 21 | GND | - | |||||||||||
22 | GND | - | 22 | GND | - | |||||||||||
23 | I/O | 21 | 39 | 汎用IO | 23 | I/O | 75 | 104 | 汎用IO | 7DLED1_A | Out | |||||
24 | I/O | 26 | 40 | 汎用IO | 24 | I/O | 74 | 103 | 汎用IO | 7DLED2_B | Out | |||||
25 | I/O | 27 | 41 | 汎用IO | 25 | I/O | 73 | 102 | 汎用IO | 7DLED3_C | Out | |||||
26 | I/O | 28 | 42 | 汎用IO | SCK | Out | 26 | I/O | 72 | 101 | 汎用IO | 7DLED4_D | Out | |||
27 | I/O | 29 | 43 | 汎用IO | 27 | I/O | 71 | 98 | 汎用IO | 7DLED5_E | Out | |||||
28 | I/O | 30 | 44 | 汎用IO | 28 | I/O | 70 | 97 | 汎用IO | 7DLED6_F | Out | |||||
29 | I/O | 33 | 45 | 汎用IO | 29 | I/O | 69 | 96 | 汎用IO | 7DLED7_G | Out | |||||
30 | I/O | 34 | 48 | 汎用IO | 30 | I/O | 68 | 95 | 汎用IO | 7DLED8_dot | Out | |||||
31 | I/O | 35 | 49 | 汎用IO | 31 | I/O | 67 | 94 | 汎用IO | |||||||
32 | I/O | 36 | 50 | 汎用IO | 32 | I/O | 66 | 93 | 汎用IO | |||||||
33 | I/O | 37 | 51 | 汎用IO | 33 | I | 64 | 91 | 入力専用端子 | |||||||
34 | I/O | 38 | 52 | 汎用IO | 34 | I | 62 | 89 | 入力専用端子 | |||||||
35 | I/O | 39 | 53 | 汎用IO | 35 | I/O | 61 | 87 | 汎用IO | SEL1 | Out | |||||
36 | I/O | 40 | 55 | 汎用IO | LCLK | In | 36 | I/O | 58 | 86 | 汎用IO | SEL2 | Out | |||
37 | GND | - | 37 | GND | - | |||||||||||
38 | GND | - | 38 | GND | - | |||||||||||
39 | I/O | 41 | 57 | 汎用IO | NFRAME | SW1 | In | 39 | I/O | 57 | 81 | 汎用IO | SEL3 | Out | ||
40 | I/O | 42 | 58 | 汎用IO | 40 | I/O | 56 | 80 | 汎用IO | SEL4 | Out | |||||
D4 | I/O | 100 | 66 | 汎用IO | LEDEN | LED4 | Out | 4 | I/O | 144 | 汎用IO | SW4 | In | |||
D3 | I/O | 99 | 63 | 汎用IO | EN80 | LED3 | Out | 3 | I/O | 143 | 汎用IO | SW3 | In | |||
D2 | I/O | 98 | 62 | 汎用IO | WRCYC | LED2 | Out | 2 | I/O | 142 | 汎用IO | SW2 | In | |||
D1 | I/O | 97 | 59 | 汎用IO | NFRAME | LED1 | Out | 1 | I/O | 144 | 汎用IO | SW1 | In |
CLK | Input | PIN_55 | 1 | PIN_55 | 3.3-V LVCMOS | 8mA (default) | |||
COMOUT[3] | Output | PIN_144 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
COMOUT[2] | Output | PIN_76 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
COMOUT[1] | Output | PIN_2 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
COMOUT[0] | Output | PIN_49 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
CS_COUNTER[4] | Output | PIN_51 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
CS_COUNTER[3] | Output | PIN_53 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
CS_COUNTER[2] | Output | PIN_50 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
CS_COUNTER[1] | Output | PIN_58 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
CS_COUNTER[0] | Output | PIN_61 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
DSEL[2] | Output | PIN_110 | 2 | PIN_110 | 3.3-V LVCMOS | 8mA (default) | |||
DSEL[1] | Output | PIN_111 | 2 | PIN_111 | 3.3-V LVCMOS | 8mA (default) | |||
DSEVEN_SEG_DATA[7] | Output | PIN_95 | 2 | PIN_95 | 3.3-V LVCMOS | 8mA (default) | |||
DSEVEN_SEG_DATA[6] | Output | PIN_96 | 2 | PIN_96 | 3.3-V LVCMOS | 8mA (default) | |||
DSEVEN_SEG_DATA[5] | Output | PIN_97 | 2 | PIN_97 | 3.3-V LVCMOS | 8mA (default) | |||
DSEVEN_SEG_DATA[4] | Output | PIN_98 | 2 | PIN_98 | 3.3-V LVCMOS | 8mA (default) | |||
DSEVEN_SEG_DATA[3] | Output | PIN_101 | 2 | PIN_101 | 3.3-V LVCMOS | 8mA (default) | |||
DSEVEN_SEG_DATA[2] | Output | PIN_102 | 2 | PIN_102 | 3.3-V LVCMOS | 8mA (default) | |||
DSEVEN_SEG_DATA[1] | Output | PIN_103 | 2 | PIN_103 | 3.3-V LVCMOS | 8mA (default) | |||
DSEVEN_SEG_DATA[0] | Output | PIN_104 | 2 | PIN_104 | 3.3-V LVCMOS | 8mA (default) | |||
EN80 | Output | PIN_66 | 1 | PIN_66 | 3.3-V LVCMOS | 8mA (default) | |||
LADCOM[3] | Input | PIN_119 | 2 | PIN_119 | 3.3-V LVCMOS | 8mA (default) | |||
LADCOM[2] | Input | PIN_118 | 2 | PIN_118 | 3.3-V LVCMOS | 8mA (default) | |||
LADCOM[1] | Input | PIN_113 | 2 | PIN_113 | 3.3-V LVCMOS | 8mA (default) | |||
LADCOM[0] | Input | PIN_112 | 2 | PIN_112 | 3.3-V LVCMOS | 8mA (default) | |||
LEDEN | Output | PIN_63 | 1 | PIN_63 | 3.3-V LVCMOS | 8mA (default) | |||
NFRAME | Output | PIN_59 | 1 | PIN_59 | 3.3-V LVCMOS | 8mA (default) | |||
NISAIOWR | Output | PIN_60 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[16] | Output | PIN_75 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[15] | Output | PIN_39 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[14] | Output | PIN_15 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[13] | Output | PIN_52 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[12] | Output | PIN_78 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[11] | Output | PIN_14 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[10] | Output | PIN_117 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[9] | Output | PIN_131 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[8] | Output | PIN_73 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[7] | Output | PIN_143 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[6] | Output | PIN_4 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[5] | Output | PIN_3 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[4] | Output | PIN_16 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[3] | Output | PIN_5 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[2] | Output | PIN_88 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[1] | Output | PIN_72 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NRCOUNTER[0] | Output | PIN_45 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
NSCK | Output | PIN_44 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
POSTDATA[7] | Output | PIN_21 | 1 | PIN_21 | 3.3-V LVCMOS | 8mA (default) | |||
POSTDATA[6] | Output | PIN_22 | 1 | PIN_22 | 3.3-V LVCMOS | 8mA (default) | |||
POSTDATA[5] | Output | PIN_23 | 1 | PIN_23 | 3.3-V LVCMOS | 8mA (default) | |||
POSTDATA[4] | Output | PIN_24 | 1 | PIN_24 | 3.3-V LVCMOS | 8mA (default) | |||
POSTDATA[3] | Output | PIN_27 | 1 | PIN_27 | 3.3-V LVCMOS | 8mA (default) | |||
POSTDATA[2] | Output | PIN_28 | 1 | PIN_28 | 3.3-V LVCMOS | 8mA (default) | |||
POSTDATA[1] | Output | PIN_29 | 1 | PIN_29 | 3.3-V LVCMOS | 8mA (default) | |||
POSTDATA[0] | Output | PIN_30 | 1 | PIN_30 | 3.3-V LVCMOS | 8mA (default) | |||
RST | Input | PIN_20 | 1 | PIN_20 | 3.3-V LVCMOS | 8mA (default) | |||
RXD | Input | PIN_32 | 1 | PIN_32 | 3.3-V LVCMOS | 8mA (default) | |||
SCK | Output | PIN_42 | 1 | PIN_42 | 3.3-V LVCMOS | 8mA (default) | |||
SCK2 | Output | PIN_106 | 3.3-V LVCMOS (default) | 8mA (default) | |||||
SEL[4] | Output | PIN_80 | 2 | PIN_80 | 3.3-V LVCMOS | 8mA (default) | |||
SEL[3] | Output | PIN_81 | 2 | PIN_81 | 3.3-V LVCMOS | 8mA (default) | |||
SEL[2] | Output | PIN_86 | 2 | PIN_86 | 3.3-V LVCMOS | 8mA (default) | |||
SEL[1] | Output | PIN_87 | 2 | PIN_87 | 3.3-V LVCMOS | 8mA (default) | |||
SEVEN_SEG_DATA[7] | Output | PIN_120 | 2 | PIN_120 | 3.3-V LVCMOS | 8mA (default) | |||
SEVEN_SEG_DATA[6] | Output | PIN_121 | 2 | PIN_121 | 3.3-V LVCMOS | 8mA (default) | |||
SEVEN_SEG_DATA[5] | Output | PIN_122 | 2 | PIN_122 | 3.3-V LVCMOS | 8mA (default) | |||
SEVEN_SEG_DATA[4] | Output | PIN_125 | 2 | PIN_125 | 3.3-V LVCMOS | 8mA (default) | |||
SEVEN_SEG_DATA[3] | Output | PIN_127 | 2 | PIN_127 | 3.3-V LVCMOS | 8mA (default) | |||
SEVEN_SEG_DATA[2] | Output | PIN_129 | 2 | PIN_129 | 3.3-V LVCMOS | 8mA (default) | |||
SEVEN_SEG_DATA[1] | Output | PIN_132 | 2 | PIN_132 | 3.3-V LVCMOS | 8mA (default) | |||
SEVEN_SEG_DATA[0] | Output | PIN_133 | 2 | PIN_133 | 3.3-V LVCMOS | 8mA (default) | |||
SW1 | Input | PIN_57 | 1 | PIN_57 | 3.3-V LVCMOS | 8mA (default) | |||
TXD | Output | PIN_31 | 1 | PIN_31 | 3.3-V LVCMOS | 8mA (default) | |||
WRCYC | Output | PIN_62 | 1 | PIN_62 | 3.3-V LVCMOS | 8mA (default) |
module LPC_PORT80h_translator1( CLK, //standard clock RST,//RST Input LADCOM,//LAD Input, SW1,//Manual Input or NFRAME NRCOUNTER, NFRAME, COMOUT, SCK, NSCK, SCK2, WRCYC, SEVEN_SEG_DATA, SEL, DSEL, DSEVEN_SEG_DATA, CS_COUNTER, POSTDATA, EN80, NISAIOWR, LEDEN, TXD, RXD ); // input definition// input CLK; input RST; input[3:0] LADCOM; input SW1;//Manual Input or NFRAME //output definition// output[16:0] NRCOUNTER; output NFRAME; output SCK; output NSCK; output SCK2; output[3:0] COMOUT; output reg WRCYC; output [4:1] SEL; output reg[7:0] SEVEN_SEG_DATA; output [2:1] DSEL; output reg[7:0] DSEVEN_SEG_DATA; output [4:0] CS_COUNTER; output[7:0] POSTDATA; output EN80; output NISAIOWR; output LEDEN; output TXD; input RXD; // register// reg nframe; reg [24:0] sec_cnt ; reg sec1_flag ;//1秒のフラグ reg toggle_flag ; //1秒ごとにトグルするフラグ reg [24:0] sec_cnt2 ; reg sec1_flag2 ;//1秒のフラグ reg toggle_flag2 ; //1秒ごとにトグルするフラグ reg sw1; reg[5:0] sw1_counter; reg[16:0] rcounter_reg; reg[16:0] rcounter; reg[16:0] cn; reg[16:0] cnp; reg[3:0] com_reg; wire[3:0] COMOUT; reg Wrcyc; reg[7:0] seven_seg1_hold; reg[7:0] seven_seg2_hold; reg[7:0] seven_seg3_hold; reg[7:0] seven_seg4_hold; reg[7:0] seven_seg_data; reg[4:1]sel; reg[1:0]enable_seg; reg[2:1]dsel; reg denable_seg; reg[7:0] dseven_seg1_hold; reg[7:0] dseven_seg2_hold; reg[4:0] cs_counter; reg[3:0] ad1; reg[3:0] ad2; reg[3:0] ad3; reg[3:0] ad4; reg[15:0] ad; reg en80; reg[3:0] ld1; reg[3:0] ld2; reg[7:0] ld; reg startflag; reg startflagen; reg nisaiowr; reg leden; wire TXD; //Serial I/F resister below// reg[10:0] CLK_COUNT; wire SHIFT_CLK; reg SEND_SW0; reg SEND_SW1; reg SEND_START; reg[8:0] SEND_REG; reg[3:0] SEND_BITCNT; reg SEND_ACTIVE; reg shift_flag1; reg toggle_flag1; //***parameter definition***// // parameter F40M0000_cnt2=24'h000001 ; //0.00000025sec interval parameter F40M0000_cnt2=24'h000FA0 ; //0.0005sec interval9600bps parameter selinit_value = 4'b0001 ; parameter dselinit_value =2'b01; parameter sw1init_value =1'b1; parameter ld1init_value =4'b1111; parameter ld2init_value =4'b1111; parameter rcounter_reg_init_value = 17'b00000000000000001; initial cs_counter = 5'b00000; initial nframe <= 1'b1 ; //Serial CLOCK// // parameter F10M0000_value=11'b01000001000;//208h 9600bps parameter F10M0000_value=11'b00000101011;//2bh 115.2kbps initial CLK_COUNT = 11'b0000000000; initial toggle_flag1 = 1'b0; //***CLK Monitoring Out***// assign SCK = CLK; assign NSCK =!CLK; //***7seg Dynamic lighting SCK2 generation***// always@(posedge CLK) begin if(sec_cnt2 == F40M0000_cnt2) begin sec_cnt2 <= 24'h000000 ; //counter counting up to the parameter(refer to No 52th row) sec1_flag2 <= 1'b1; end else begin sec_cnt2 <= sec_cnt2 + 1 ; sec1_flag2 <= 1'b0 ; end end always@(posedge CLK) begin if(sec1_flag2 == 1'b1 )begin toggle_flag2 <= !toggle_flag2 ; end end assign SCK2 =!toggle_flag2; //***end***// always@(posedge NSCK or negedge RST) begin if(RST ==1'b0)begin sw1_counter <= 5'b00000; end else begin sw1_counter <= sw1_counter +1'b1; end end always@(SW1) begin if(RST ==1'b0)begin sw1 <= 1'b1; end else if(CLK ==1'b1)begin sw1 <=SW1; //nframe <= sw1; end end assign NFRAME = ~nframe; // ***RING COUNTER***// always@(posedge CLK or negedge RST or posedge nframe) begin if(RST == 1'b0 ) begin rcounter_reg <= 16'h0 ; end else if(nframe ==1'b1)begin//1'b1 rcounter_reg <= 16'h0 ; end else begin rcounter_reg <= rcounter_reg <<1; rcounter_reg [0] <= rcounter[16]; end end always@* begin rcounter[16] <= ~|rcounter_reg;//16 rcounter[15:0]<=rcounter_reg; cn<=~rcounter_reg; cnp<=~cn; end // assign NRCOUNTER = cn; // always@(posedge NSCK or negedge RST )//SCK always@(posedge CLK or negedge RST or negedge SW1)//SCK begin if(RST == 1'b0 )begin cs_counter<= 5'b00000; end else if(SW1 == 1'b0)begin cs_counter <=5'b00000; end else if(cs_counter > 5'b10001)begin cs_counter <=5'b00000; end else begin cs_counter <= cs_counter +1'b1; end end always@* begin if(RST == 1'b0)begin nframe<= 1'b1; end else if(SW1 ==1'b0)begin nframe <= 1'b1; end else if(cs_counter >5'b01011)begin//1101 nframe <=1'b1; end else begin nframe <=1'b0; end end assign CS_COUNTER = cs_counter; always@(negedge RST or posedge CLK) begin if(RST == 1'b0)begin startflag <=1'b0; end else if(SW1 == 1'b0) begin if(LADCOM[3:0] == 4'b0000) startflag <= 1'b1; end else begin startflag <= 1'b0; end end always@(negedge RST or posedge SW1) begin if(RST == 1'b0)begin startflagen <=1'b0; end else if(startflag ==1'b0) begin startflagen <= 1'b0; end else begin startflagen <= 1'b1; end end always@( negedge RST or negedge SW1 or posedge LADCOM[3:0] or posedge CLK or posedge startflag )//negedge SCK or negedge cn[0] begin if(RST ==1'b0)begin com_reg <=1'b0; end else if(startflag ==1'b1 )begin // if(SCK ==1'b1) case(LADCOM) 4'b0000 : com_reg<= 1'b0; //'0' 4'b0001 : com_reg <= 1'b0; //'1' 4'b0010 : com_reg <= 1'b1; //'1' 4'b0011 : com_reg<= 1'b0; //'0' 4'b0100 : com_reg<= 1'b0 ; //'0' 4'b0101 : com_reg <= 1'b0; //'1' 4'b0110 : com_reg<= 1'b0; //'0' 4'b0111 : com_reg<= 1'b0 ; //'0' 4'b1000 : com_reg<= 1'b0 ; //'0' 4'b1001 : com_reg <= 1'b0; //'1' 4'b1010 : com_reg<= 1'b0; //'0' 4'b1011 : com_reg<= 1'b0 ; //'0' 4'b1100 : com_reg<= 1'b0 ; //'0' 4'b1101 : com_reg<= 1'b0 ; //'0' 4'b1110 : com_reg <= 1'b0; //'1' 4'b1111 : com_reg<= 1'b0; //'0' default: com_reg<= 1'b0 ; //'0' endcase end end assign COMOUT =com_reg; always@( negedge RST or negedge SW1 or posedge LADCOM[3:0] or posedge CLK or posedge startflag)//negedge SCK or negedge cn[0] begin if(RST ==1'b0)begin Wrcyc <=1'b0; end else if(startflag ==1'b1 )begin //if(SCK ==1'b1) case(LADCOM) 4'b0000 : Wrcyc<= 1'b0; //'0' 4'b0001 : Wrcyc <= 1'b0; //'1' 4'b0010 : Wrcyc <= 1'b1; //'1' 4'b0011 : Wrcyc<= 1'b0; //'0' 4'b0100 : Wrcyc<= 1'b0 ; //'0' 4'b0101 : Wrcyc <= 1'b0; //'1' 4'b0110 : Wrcyc<= 1'b0; //'0' 4'b0111 : Wrcyc<= 1'b0 ; //'0' 4'b1000 : Wrcyc<= 1'b0 ; //'0' 4'b1001 : Wrcyc <= 1'b0; //'1' 4'b1010 : Wrcyc<= 1'b0; //'0' 4'b1011 : Wrcyc<= 1'b0 ; //'0' 4'b1100 : Wrcyc<= 1'b0 ; //'0' 4'b1101 : Wrcyc<= 1'b0 ; //'0' 4'b1110 : Wrcyc <= 1'b0; //'1' 4'b1111 : Wrcyc<= 1'b0; //'0' default: Wrcyc<= 1'b0 ; //'0' endcase end end always@(posedge Wrcyc or negedge SW1) begin if(SW1 ==1'b0)begin WRCYC <=1'b0; end else begin WRCYC <= ~nframe; end end always@(negedge RST or posedge cn[5] or negedge cn[9]) begin if(RST ==1'b0)begin nisaiowr <=1'b1; end else if(cn[9] ==1'b0)begin nisaiowr <=1'b1; end else if(cn[5] == 1'b1)begin nisaiowr <=1'b0; end end
assign NISAIOWR = nisaiowr ; always@(posedge SCK2 or negedge RST)begin if(RST == 1'b0 )begin sel <= selinit_value; end else begin sel[4] <= sel[1] ; //シフト動作を開始する sel[3] <= sel[4] ; //シフト動作を開始する sel[2] <= sel[3] ; //シフト動作を開始する sel[1] <= sel[2] ; end end assign SEL[4:1] = ~sel[4:1]; always@(negedge RST or posedge CLK or posedge leden)//posedge cnp[0] //* always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[1] or posedge SCK) begin if(RST ==1'b0)begin seven_seg1_hold <=8'b00000110; end else if(leden==1'b1 )begin//cnp[0]==1'b1 // if(SCK ==1'b1&& WRCYC==1'b1 && startflagen ==1'b1) //if( WRCYC==1'b1) case(ad1)//LADCOM 4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0' dot g f e d c b a 4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1' 4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2' 4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3' 4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4' 4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5' 4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6' 4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7' 4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8' 4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9' 4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A' 4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b' 4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c' 4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d' 4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E' 4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F' default: seven_seg1_hold <= 8'b01110001; endcase end end always@(negedge RST or posedge CLK or posedge leden)//posedge cnp[1] //always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[2] or posedge SCK) begin if(RST ==1'b0)begin seven_seg2_hold <=8'b01011011; end else if(leden==1'b1)begin//cnp[1]==1'b1 //if(WRCYC==1'b1) case(ad2) 4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0 4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1' 4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2' 4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3' 4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4' 4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5' 4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6' 4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7' 4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8' 4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9' 4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A' 4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b' 4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c' 4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d' 4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E' 4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F' default: seven_seg2_hold <= 8'b01110001; endcase end end always@(negedge RST or posedge CLK or posedge leden)//posedge cnp[2] //always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[3] or posedge SCK) begin if(RST ==1'b0)begin seven_seg3_hold <=8'b01001111; end else if(leden==1'b1)begin //if(WRCYC==1'b1) case(ad3) 4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0' 4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1' 4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2' 4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3' 4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4' 4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5' 4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6' 4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7' 4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8' 4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9' 4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A' 4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b' 4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c' 4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d' 4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E' 4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F' default: seven_seg3_hold <= 8'b01110001; endcase end end always@(negedge RST or posedge CLK or posedge leden) //always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[4] or posedge SCK) begin if(RST ==1'b0)begin seven_seg4_hold <=8'b01100110; end else if(leden==1'b1)begin // if(WRCYC==1'b1) case(ad4) 4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0' 4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1' 4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2' 4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3' 4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4' 4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5' 4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6' 4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7' 4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8' 4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9' 4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A' 4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b' 4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c' 4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d' 4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E' 4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F' default: seven_seg4_hold <= 8'b01110001; endcase end end always@(negedge RST or posedge CLK or posedge cnp[0]) begin if(RST ==1'b0)begin ad1 <=4'b0000; end else if(cnp[0]==1'b1)begin if(WRCYC==1'b1) ad1 <= LADCOM; end end always@(negedge RST or posedge CLK or posedge cnp[1]) begin if(RST ==1'b0)begin ad2 <=4'b0000; end else if(cnp[1]==1'b1)begin if(WRCYC==1'b1) ad2 <= LADCOM; end end always@(negedge RST or posedge CLK or posedge cnp[2]) begin if(RST ==1'b0)begin ad3 <=4'b0000; end else if(cnp[2]==1'b1)begin if(WRCYC==1'b1) ad3 <= LADCOM; end end always@(negedge RST or posedge CLK or posedge cnp[3]) begin if(RST ==1'b0)begin ad4 <=4'b0000; end else if(cnp[3]==1'b1)begin if(WRCYC==1'b1) ad4 <= LADCOM; end end always@(negedge RST or posedge CLK or posedge cnp[4]) begin if(RST ==1'b0)begin ad <=16'h0000; end else if(cnp[4]==1'b1)begin if(WRCYC==1'b1) ad <={ad1,ad2,ad3,ad4}; end end always@(negedge RST or posedge CLK or posedge cnp[5]) begin if(RST ==1'b0)begin ld1 <=4'b0000; end else if(cnp[5]==1'b1)begin if(WRCYC==1'b1) ld1 <= LADCOM; end end always@(negedge RST or posedge CLK or posedge cnp[4]) begin if(RST ==1'b0)begin ld2 <=4'b0000; end else if(cnp[4]==1'b1)begin if(WRCYC==1'b1 ) ld2 <=LADCOM; end end always@(negedge RST or posedge CLK or posedge leden)//posedge cnp[5] begin if(RST ==1'b0)begin ld <=8'b00000000; end else if(leden ==1'b1)begin ld <={ld1,ld2}; end end assign POSTDATA = ld; always@(negedge RST or negedge SW1 or negedge cn[7]) begin if(RST ==1'b0)begin en80 <=1'b0; end else if(SW1==1'b0)begin en80 <=1'b0; end else if(WRCYC==1'b1 && ad == 16'h0080)begin en80<=1'b1; end else begin en80<=1'b0; end end assign EN80 = ~en80; always@(negedge en80 or posedge CLK or posedge ad[0] or posedge nisaiowr) begin if(en80 ==1'b0)begin leden <=1'b0; end else if(ad[0] ==1'b1)begin leden <=1'b0; end else if(nisaiowr ==1'b1)begin leden <=1'b0; end else begin leden <=1'b1; end end assign LEDEN = ~leden; always@(posedge SCK2 or negedge RST)begin if(RST == 1'b0 )begin enable_seg <= 2'b00; end else begin enable_seg <= enable_seg +1'b1; end end always@* //* whenever inputs change, holding counter value as the resister "SEVEN_SEG_DATA" begin case(enable_seg) 2'b00: SEVEN_SEG_DATA <= ~seven_seg4_hold; 2'b01: SEVEN_SEG_DATA<=~seven_seg1_hold; 2'b10: SEVEN_SEG_DATA<=~seven_seg2_hold; 2'b11: SEVEN_SEG_DATA<=~seven_seg3_hold; default SEVEN_SEG_DATA<=8'b11111111; endcase end always@(negedge RST or posedge SCK2) begin if(RST == 1'b0 )begin dsel <= dselinit_value; end else begin dsel[2]<=dsel[1] ; //シフト動作を開始する dsel[1] <= dsel[2] ; //シフト動作を開始する end end assign DSEL[2:1] =~dsel[2:1]; //always@(negedge RST or posedge en80) //cn6 // always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[5] or posedge SCK) always@(negedge RST or posedge leden or posedge CLK) begin if(RST ==1'b0)begin dseven_seg1_hold <=8'b01011011; end else if(leden == 1'b1 )begin//en80 // if(SCK ==1'b1 && WRCYC==1'b1 && startflagen ==1'b1 ) case(ld2)//LADCOM 4'b0000 : dseven_seg1_hold<= 8'b00111111 ; //'0' dot g f e d c b a 4'b0001 : dseven_seg1_hold <= 8'b00000110 ; //'1' 4'b0010 : dseven_seg1_hold<= 8'b01011011 ; //'2' 4'b0011 : dseven_seg1_hold <= 8'b01001111 ; //'3' 4'b0100 : dseven_seg1_hold <= 8'b01100110 ; //'4' 4'b0101 : dseven_seg1_hold <= 8'b01101101 ; //'5' 4'b0110 : dseven_seg1_hold <= 8'b01111101 ; //'6' 4'b0111 : dseven_seg1_hold <= 8'b00100111 ; //'7' 4'b1000 : dseven_seg1_hold <= 8'b01111111 ; //'8' 4'b1001 : dseven_seg1_hold <= 8'b01101111 ; //'9' 4'b1010 : dseven_seg1_hold <= 8'b01110111 ; //'A' 4'b1011 : dseven_seg1_hold <= 8'b01111100 ; //'b' 4'b1100 : dseven_seg1_hold <= 8'b01011000 ; //'c' 4'b1101 : dseven_seg1_hold <= 8'b01011110 ; //'d' 4'b1110 : dseven_seg1_hold <= 8'b01111001 ; //'E' 4'b1111 : dseven_seg1_hold <= 8'b01110001 ; //'F' default: dseven_seg1_hold <= 8'b01110001; endcase end end //always@(negedge RST or posedge en80) //5 //always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[6] or posedge SCK) always@(negedge RST or posedge leden or posedge CLK) begin if(RST ==1'b0)begin dseven_seg2_hold <=8'b00000110; end else if(leden == 1'b1)begin//en80 // if(SCK ==1'b1 && WRCYC==1'b1 && startflagen ==1'b1) case(ld1) 4'b0000 : dseven_seg2_hold<= 8'b00111111 ; //'0 4'b0001 : dseven_seg2_hold <= 8'b00000110 ; //'1' 4'b0010 : dseven_seg2_hold<= 8'b01011011 ; //'2' 4'b0011 : dseven_seg2_hold <= 8'b01001111 ; //'3' 4'b0100 : dseven_seg2_hold <= 8'b01100110 ; //'4' 4'b0101 : dseven_seg2_hold <= 8'b01101101 ; //'5' 4'b0110 : dseven_seg2_hold <= 8'b01111101 ; //'6' 4'b0111 : dseven_seg2_hold <= 8'b00100111 ; //'7' 4'b1000 : dseven_seg2_hold <= 8'b01111111 ; //'8' 4'b1001 : dseven_seg2_hold <= 8'b01101111 ; //'9' 4'b1010 : dseven_seg2_hold <= 8'b01110111 ; //'A' 4'b1011 : dseven_seg2_hold <= 8'b01111100 ; //'b' 4'b1100 : dseven_seg2_hold <= 8'b01011000 ; //'c' 4'b1101 : dseven_seg2_hold <= 8'b01011110 ; //'d' 4'b1110 : dseven_seg2_hold <= 8'b01111001 ; //'E' 4'b1111 : dseven_seg2_hold <= 8'b01110001 ; //'F' default: dseven_seg2_hold <= 8'b01110001; endcase end end always@(posedge SCK2 or negedge RST)begin if(RST == 1'b0 )begin denable_seg <= 1'b0; end else begin denable_seg <= denable_seg +1'b1; end end always@* //* whenever inputs change, holding counter value as the resister "SEVEN_SEG_DATA" begin case(denable_seg) 1'b0: DSEVEN_SEG_DATA <= ~dseven_seg2_hold; 1'b1: DSEVEN_SEG_DATA<=~dseven_seg1_hold; default DSEVEN_SEG_DATA<=8'b11111111; endcase end // assign SEVEN_SEG_DATA = seven_seg_data; //Serial I/F below// always@(posedge CLK ) begin if(CLK_COUNT == F10M0000_value) begin //1A0 CLK_COUNT <= 11'b0000000000; shift_flag1 <= 1'b1; end else begin CLK_COUNT <= CLK_COUNT + 1; shift_flag1 <= 1'b0; end end always@(posedge CLK) begin if(shift_flag1 == 1'b1)begin toggle_flag1 <= !toggle_flag1; end end assign SHIFT_CLK = !toggle_flag1; always@(posedge SHIFT_CLK or negedge RST) begin if(RST == 1'b0)begin SEND_START <= 1'b0 ; SEND_SW1 <= 1'b0; SEND_SW0 <= 1'b0; end else begin if(SEND_SW1 == 1'b0 & SEND_SW0 == 1'b1)begin SEND_START <= 1'b1; end else begin SEND_START <= 1'b0; end SEND_SW1 <= SEND_SW0; SEND_SW0 <= LEDEN; end end
always@(posedge SHIFT_CLK or negedge RST) begin if(RST == 1'b0)begin SEND_REG <= 9'b111111111; SEND_BITCNT <= 4'b0000; SEND_ACTIVE <= 1'b0; end else begin if(SEND_ACTIVE == 1'b0)begin if(SEND_START == 1'b1)begin SEND_REG[8:1] <= ld;//8'b01000001; //41h(LSB first) SEND_REG[0] <= 1'b0; SEND_BITCNT <= 4'b0000; SEND_ACTIVE <= 1'b1; end end else begin SEND_REG[8] <= 1'b1; SEND_REG[7:0] <= SEND_REG[8:1]; if(SEND_BITCNT == 4'b1001)begin SEND_ACTIVE <= 1'b0; end else begin SEND_BITCNT <= SEND_BITCNT + 1; end end end end assign TXD = SEND_REG[0]; endmodule
`timescale 1 ns/ 1 ns module LPC_PORT80h_translator1_vlg_tst(); // constants // general purpose registers reg eachvec; // test vector input registers reg CLK; reg [3:0] LADCOM; reg RST; reg SW1; reg RXD; // wires wire [3:0] COMOUT; wire [4:0] CS_COUNTER; wire [2:1] DSEL; wire [7:0] DSEVEN_SEG_DATA; wire NFRAME; wire [16:0] NRCOUNTER; wire NSCK; wire SCK; wire SCK2; wire [4:1] SEL; wire [7:0] SEVEN_SEG_DATA; wire WRCYC; wire [7:0] POSTDATA; wire TXD; parameter STEP1 = 500; // ns parameter STEP2 = 10; //ns 33MHz // assign statements (if any) LPC_PORT80h_translator1 i1 ( // port map - connection between master ports and signals/registers .CLK(CLK), .COMOUT(COMOUT), .CS_COUNTER(CS_COUNTER), .DSEL(DSEL), .DSEVEN_SEG_DATA(DSEVEN_SEG_DATA), .LADCOM(LADCOM), .NFRAME(NFRAME), .NRCOUNTER(NRCOUNTER), .NSCK(NSCK), .RST(RST), .SCK(SCK), .SCK2(SCK2), .SEL(SEL), .SEVEN_SEG_DATA(SEVEN_SEG_DATA), .SW1(SW1), .WRCYC(WRCYC), .POSTDATA(POSTDATA), .EN80(EN80), .NISAIOWR(NISAIOWR), .LEDEN(LEDEN), .TXD(TXD), .RXD(RXD) ); initial begin RST <=1'b0; CLK <=1'b0; SW1 <= 1'b1; //1 //RST deassert SW1(frame) assert addr 80h data 5Ah #0 LADCOM[3:0] <=4'b0000; //1 start #1 SW1 <= 1'b0; #0 RST <= 1'b1; #9 SW1 <=1'b1; #0 LADCOM[3:0] <=4'b0010; // 2 command #10 LADCOM[3:0] <=4'b0000;//0x0 3 addr1 #10 LADCOM[3:0] <=4'b0000;//0x0 4 addr2 #10 LADCOM[3:0] <=4'b1000;//0x8 5 addr3 #10 LADCOM[3:0] <=4'b0000;//0x0 6 addr4 #10 LADCOM[3:0] <=4'b1010;//0xA 7 data1 #10 LADCOM[3:0] <=4'b0101;//0x5 8 data2 #10 LADCOM[3:0] <=4'b0001;//0x1 9 #10 LADCOM[3:0] <=4'b0010;//0x2 10 #10 LADCOM[3:0] <=4'b0100;//0x8 11 #10 LADCOM[3:0] <=4'b1111;//0xf 12 #10 LADCOM[3:0] <=4'b1101;//0xf 13 #10 //RST deassert SW1(frame) assert addr f359h data 21h #10 RST <= 1'b0; #10 RST <= 1'b1; #10 SW1 <= 1'b0; #0 LADCOM[3:0] <=4'b0000; //0x0 1 #10 SW1 <=1'b1; #0 LADCOM[3:0] <=4'b0010; //0x0 2 #10 LADCOM[3:0] <=4'b1111;//0xf 3 addr1 #10 LADCOM[3:0] <=4'b0011;//0x3 4 addr2 #10 LADCOM[3:0] <=4'b0101;//0x5 5 addr3 #10 LADCOM[3:0] <=4'b1001;//0x9 6 addr4 #10 LADCOM[3:0] <=4'b0000;//0x1 7 data1 #10 LADCOM[3:0] <=4'b0010;//0x2 8 data2 #10 LADCOM[3:0] <=4'b0001;// 9 #10 LADCOM[3:0] <=4'b0010;// 10 #10 LADCOM[3:0] <=4'b0100;// 11 #10 LADCOM[3:0] <=4'b1111;// 12 #10 LADCOM[3:0] <=4'b1101;// 13 #10 //SW1(frame) assert addr 0081h data 76h #10 SW1 <= 1'b0; #0 LADCOM[3:0] <=4'b0000; //1 #10 SW1 <=1'b1; #0 LADCOM[3:0] <=4'b0000; //0x0 command 0 #10 LADCOM[3:0] <=4'b0000;//0x1 addr1 0 #10 LADCOM[3:0] <=4'b1000;//0x2 addr2 8 #10 LADCOM[3:0] <=4'b0001;//0x4 addr3 1 #10 LADCOM[3:0] <=4'b1000;//0x8 addr4 6 #10 LADCOM[3:0] <=4'b0000;//0x1 data1 7 #10 LADCOM[3:0] <=4'b0010;//0x2 data2 8 #10 LADCOM[3:0] <=4'b0001;// 9 #10 LADCOM[3:0] <=4'b0010;// 10 #10 LADCOM[3:0] <=4'b0100;// 11 #10 LADCOM[3:0] <=4'b1111;// 12 #10 LADCOM[3:0] <=4'b1101;// 13 #10 //SW1(frame) assert addr 0080h data bah #10 SW1 <= 1'b0; #0 LADCOM[3:0] <=4'b0000; // 1 #10 SW1 <=1'b1; #0 LADCOM[3:0] <=4'b0010; //0x2 2 #10 LADCOM[3:0] <=4'b0000;//0x0 3 #10 LADCOM[3:0] <=4'b0000;//0x0 4 #10 LADCOM[3:0] <=4'b1000;//0x8 5 #10 LADCOM[3:0] <=4'b0000;//0x0 6 #10 LADCOM[3:0] <=4'b1010;//0xa 7 #10 LADCOM[3:0] <=4'b1011;//0xb 8 #10 LADCOM[3:0] <=4'b1100;//0xc 9 #10 LADCOM[3:0] <=4'b1101;//0xd 10 #10 LADCOM[3:0] <=4'b1110;//0xe 11 #10 LADCOM[3:0] <=4'b1111;//0xf 12 #10 LADCOM[3:0] <=4'b1101;//0xf 13 // code that executes only once // insert code here --> begin // --> end $display("Running testbench"); end //always#(STEP1/2) //begin //RST <= ~RST; //end always#(STEP2/2) begin CLK <= ~CLK; end // optional sensitivity list // @(event1 or event2 or .... eventn) //begin // code executes for every event on sensitivity list // insert code here --> begin //@eachvec; // --> end //end endmodule