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1.PORT80h DECODER
1-1.タイミングチャート
1-2.ピン一覧
1-3.ソースコード
1-4.テストベンチソースコード
下記のような構成を考える。
CN1 | CN2 | |||||||||||||
Pin | 番号 | 種別 | CPLD | 信号名 | 基板上LED | In/Out | Pin | 番号 | 説明 | Pin | 信号名 | 基板上LED | In/Out | |
1 | VCC_A | - | +3.3V | +3.3V | - | 1 | VCC_B | - | +3.3V | +3.3V | - | |||
2 | VCC_A | - | +3.3V | +3.3V | - | 2 | VCC_B | - | +3.3V | +3.3V | - | |||
3 | GND | - | GND | - | 3 | GND | - | GND | - | |||||
4 | GND | - | GND | - | 4 | GND | - | GND | - | |||||
5 | I/O | 2 | 汎用IO | LED15 | LEDC15 | 5 | I/O | 91 | 汎用IO | 7LED1_A | Out | |||
6 | I | 14 | 入力専用端子 | RST | In | 6 | I/O | 90 | 汎用IO | 7LED2_B | Out | |||
7 | I/O | 3 | 汎用IO | LED14 | LEDC14 | 7 | I/O | 89 | 汎用IO | 7LED3_C | Out | |||
8 | I/O | 4 | 汎用IO | LED13 | LEDC13 | 8 | I/O | 88 | 汎用IO | 7LED4_D | Out | |||
9 | I/O | 5 | 汎用IO | LED12 | LEDC12 | 9 | I/O | 87 | 汎用IO | 7LED5_E | Out | |||
10 | I/O | 6 | 汎用IO | LED11 | LEDC11 | 10 | I/O | 86 | 汎用IO | 7LED6_F | Out | |||
11 | I/O | 7 | 汎用IO | LED10 | LEDC10 | 11 | I/O | 85 | 汎用IO | 7LED7_G | Out | |||
12 | I/O | 8 | 汎用IO | LED9 | LEDC9 | 12 | I/O | 84 | 汎用IO | 7LED8_dot | Out | |||
13 | I/O | 15 | 汎用IO | LED8 | LEDC8 | 13 | I/O | 83 | 汎用IO | LADCOM[3] | In | |||
14 | I/O | 16 | 汎用IO | LED7 | LEDC7 | 14 | I/O | 82 | 汎用IO | LADCOM[2] | In | |||
15 | I/O | 17 | 汎用IO | LED6 | LEDC6 | 15 | I/O | 81 | 汎用IO | LADCOM[1] | In | |||
16 | I/O | 18 | 汎用IO | LED5 | LEDC5 | 16 | I/O | 78 | 汎用IO | LADCOM[0] | In | |||
17 | I/O | 19 | 汎用IO | LED4 | LEDC4 | 17 | I/O | 77 | 汎用IO | DSEL1 | ||||
18 | I/O | 20 | 汎用IO | LED3 | LEDC3 | 18 | I/O | 76 | 汎用IO | DSEL2 | ||||
19 | GND | - | 19 | GND | - | |||||||||
20 | GND | - | 20 | GND | - | |||||||||
21 | GND | - | 21 | GND | - | |||||||||
22 | GND | - | 22 | GND | - | |||||||||
23 | I/O | 21 | 汎用IO | LED2 | LEDC2 | 23 | I/O | 75 | 汎用IO | 7DLED1_A | Out | |||
24 | I/O | 26 | 汎用IO | LED1 | LEDC1 | 24 | I/O | 74 | 汎用IO | 7DLED2_B | Out | |||
25 | I/O | 27 | 汎用IO | LED0 | LEDC0 | 25 | I/O | 73 | 汎用IO | 7DLED3_C | Out | |||
26 | I/O | 28 | 汎用IO | SCK | Out | 26 | I/O | 72 | 汎用IO | 7DLED4_D | Out | |||
27 | I/O | 29 | 汎用IO | NFRAME | Out | 27 | I/O | 71 | 汎用IO | 7DLED5_E | Out | |||
28 | I/O | 30 | 汎用IO | COMOUT[3] | Out | 28 | I/O | 70 | 汎用IO | 7DLED6_F | Out | |||
29 | I/O | 33 | 汎用IO | COMOUT[2] | Out | 29 | I/O | 69 | 汎用IO | 7DLED7_G | Out | |||
30 | I/O | 34 | 汎用IO | COMOUT[1] | Out | 30 | I/O | 68 | 汎用IO | 7DLED8_dot | Out | |||
31 | I/O | 35 | 汎用IO | COMOUT[0] | Out | 31 | I/O | 67 | 汎用IO | |||||
32 | I/O | 36 | 汎用IO | RSERV | 32 | I/O | 66 | 汎用IO | ||||||
33 | I/O | 37 | 汎用IO | RSERV | 33 | I | 64 | 入力専用端子 | ||||||
34 | I/O | 38 | 汎用IO | RSERV | 34 | I | 62 | 入力専用端子 | ||||||
35 | I/O | 39 | 汎用IO | RSERV | 35 | I/O | 61 | 汎用IO | SEL1 | |||||
36 | I/O | 40 | 汎用IO | LCLK | In | 36 | I/O | 58 | 汎用IO | SEL2 | ||||
37 | GND | - | 37 | GND | - | |||||||||
38 | GND | - | 38 | GND | - | |||||||||
39 | I/O | 41 | 汎用IO | NFRAME | SW1 | In | 39 | I/O | 57 | 汎用IO | SEL3 | |||
40 | I/O | 42 | 汎用IO | 40 | I/O | 56 | 汎用IO | SEL4 |
module LPC_PORT80h_decoder7( CLK, //standard clock RST,//RESET Input LADCOM,//LAD Input, SW1,//Manual Input or NFRAME NRCOUNTER, NFRAME, COMOUT, SCK, NSCK, SCK2, WRCYC, SEVEN_SEG_DATA, SEL, DSEL, DSEVEN_SEG_DATA, CS_COUNTER ); // input definition// input CLK; input RST; input[3:0] LADCOM; input SW1;//Manual Input or NFRAME //output definition// output[16:0] NRCOUNTER; output NFRAME; output SCK; output NSCK; output SCK2; output[3:0] COMOUT; output reg WRCYC; output [4:1] SEL; output reg[7:0] SEVEN_SEG_DATA; output [2:1] DSEL; output reg[7:0] DSEVEN_SEG_DATA; output [4:0]CS_COUNTER; // register// reg nframe; reg [24:0] sec_cnt ; reg sec1_flag ;//1秒のフラグ reg toggle_flag ; //1秒ごとにトグルするフラグ reg [24:0] sec_cnt2 ; reg sec1_flag2 ;//1秒のフラグ reg toggle_flag2 ; //1秒ごとにトグルするフラグ reg sw1; reg[5:0] sw1_counter; reg[16:0] rcounter_reg; reg[16:0] rcounter; reg[16:0] cn; reg[3:0] com_reg; wire[3:0] COMOUT; reg Wrcyc; reg[7:0] seven_seg1_hold; reg[7:0] seven_seg2_hold; reg[7:0] seven_seg3_hold; reg[7:0] seven_seg4_hold; reg[7:0] seven_seg_data; reg[4:1]sel; reg[1:0]enable_seg; reg[2:1]dsel; reg denable_seg; reg[7:0] dseven_seg1_hold; reg[7:0] dseven_seg2_hold; reg tar; reg[4:0] cs_counter; reg[3:0] ad1; reg[3:0] ad2; reg[3:0] ad3; reg[3:0] ad4; reg[15:0] ad; reg en80; reg[3:0] ld1; reg[3:0] ld2; reg[7:0] ld; //***parameter definition***// //parameter F40M0000_cnt=24'h000001 ; //0.00000025sec interval parameter F40M0000_cnt2=24'h000190 ; //0.0001sec interval parameter selinit_value = 4'b0001 ; parameter dselinit_value =2'b01; parameter sw1init_value =1'b1; parameter ld1init_value =4'b1111; parameter ld2init_value =4'b1111; parameter rcounter_reg_init_value = 17'b00000000000000001; initial cs_counter = 5'b00000; initial nframe <= 1'b1 ; //***CLK Monitoring Out***// assign SCK = CLK; assign NSCK =!CLK; //***7seg Dynamic lighting SCK2 generation***// always@(posedge CLK) begin if(sec_cnt2 == F40M0000_cnt2) begin sec_cnt2 <= 24'h000000 ; //counter counting up to the parameter(refer to No 52th row) sec1_flag2 <= 1'b1; end else begin sec_cnt2 <= sec_cnt2 + 1 ; sec1_flag2 <= 1'b0 ; end end always@(posedge CLK) begin if(sec1_flag2 == 1'b1 )begin toggle_flag2 <= !toggle_flag2 ; end end assign SCK2 =!toggle_flag2; //***end***// always@(posedge NSCK or negedge RST) begin if(RST ==1'b0)begin sw1_counter <= 5'b00000; end else begin sw1_counter <= sw1_counter +1'b1; end end always@(SW1) begin if(RST ==1'b0)begin sw1 <= 1'b1; end else if(CLK ==1'b1)begin sw1 <=SW1; //nframe <= sw1; end end assign NFRAME = nframe; // ***RING COUNTER***// always@(posedge CLK or negedge RST or posedge nframe) begin if(RST == 1'b0 ) begin rcounter_reg <= 16'h0 ; end else if(nframe ==1'b1)begin//1'b1 rcounter_reg <= 16'h0 ; end else begin rcounter_reg <= rcounter_reg <<1; rcounter_reg [0] <= rcounter[16]; end end always@* begin rcounter[16] <= ~|rcounter_reg;//16 rcounter[15:0]<=rcounter_reg; cn<=~rcounter_reg; end assign NRCOUNTER = cn; // always@(posedge NSCK or negedge RST )//SCK always@(posedge CLK or negedge RST or negedge SW1)//SCK begin if(RST == 1'b0 )begin cs_counter<= 5'b00000; end else if(SW1 == 1'b0)begin cs_counter <=5'b00000; end else if(cs_counter > 5'b10001)begin cs_counter <=5'b00000; end else begin cs_counter <= cs_counter +1'b1; end end always@* begin if(RST == 1'b0)begin nframe<= 1'b1; end else if(SW1 ==1'b0)begin nframe <= 1'b1; end else if(cs_counter >5'b01011)begin nframe <=1'b1; end else begin nframe <=1'b0; end end assign CS_COUNTER = cs_counter; always@( negedge RST or negedge SW1 or posedge LADCOM[3:0] or posedge CLK or negedge SCK or negedge cn[0] )//or negedge cn[0] begin if(RST ==1'b0)begin com_reg <=1'b0; end else if(cn[0] ==1'b0 )begin if(SCK ==1'b1) case(LADCOM) 4'b0000 : com_reg<= 1'b0; //'0' 4'b0001 : com_reg <= 1'b0; //'1' 4'b0010 : com_reg <= 1'b1; //'1' 4'b0011 : com_reg<= 1'b0; //'0' 4'b0100 : com_reg<= 1'b0 ; //'0' 4'b0101 : com_reg <= 1'b0; //'1' 4'b0110 : com_reg<= 1'b0; //'0' 4'b0111 : com_reg<= 1'b0 ; //'0' 4'b1000 : com_reg<= 1'b0 ; //'0' 4'b1001 : com_reg <= 1'b0; //'1' 4'b1010 : com_reg<= 1'b0; //'0' 4'b1011 : com_reg<= 1'b0 ; //'0' 4'b1100 : com_reg<= 1'b0 ; //'0' 4'b1101 : com_reg<= 1'b0 ; //'0' 4'b1110 : com_reg <= 1'b0; //'1' 4'b1111 : com_reg<= 1'b0; //'0' default: com_reg<= 1'b0 ; //'0' endcase end end assign COMOUT =com_reg; always@( negedge RST or negedge SW1 or posedge LADCOM[3:0] or posedge CLK or negedge SCK or negedge cn[0] ) begin if(RST ==1'b0)begin Wrcyc <=1'b0; end else if(cn[0]==1'b0 )begin if(SCK ==1'b1) case(LADCOM) 4'b0000 : Wrcyc<= 1'b0; //'0' 4'b0001 : Wrcyc <= 1'b0; //'1' 4'b0010 : Wrcyc <= 1'b1; //'1' 4'b0011 : Wrcyc<= 1'b0; //'0' 4'b0100 : Wrcyc<= 1'b0 ; //'0' 4'b0101 : Wrcyc <= 1'b0; //'1' 4'b0110 : Wrcyc<= 1'b0; //'0' 4'b0111 : Wrcyc<= 1'b0 ; //'0' 4'b1000 : Wrcyc<= 1'b0 ; //'0' 4'b1001 : Wrcyc <= 1'b0; //'1' 4'b1010 : Wrcyc<= 1'b0; //'0' 4'b1011 : Wrcyc<= 1'b0 ; //'0' 4'b1100 : Wrcyc<= 1'b0 ; //'0' 4'b1101 : Wrcyc<= 1'b0 ; //'0' 4'b1110 : Wrcyc <= 1'b0; //'1' 4'b1111 : Wrcyc<= 1'b0; //'0' default: Wrcyc<= 1'b0 ; //'0' endcase end end always@(posedge Wrcyc or negedge SW1) begin if(SW1 ==1'b0)begin WRCYC <=1'b0; end else begin WRCYC <= ~nframe; end end always@( negedge RST or negedge SW1 or posedge LADCOM[3:0] or posedge CLK or negedge SCK or negedge cn[1] ) begin if(RST ==1'b0)begin tar <=1'b0; end else if(cn[1]==1'b0 )begin if(SCK ==1'b1) case(LADCOM) 4'b0000 : tar<= 1'b0; //'0' 4'b0001 : tar <= 1'b0; //'1' 4'b0010 : tar <= 1'b0; //'1' 4'b0011 : tar<= 1'b0; //'0' 4'b0100 : tar<= 1'b0 ; //'0' 4'b0101 : tar <= 1'b0; //'1' 4'b0110 : tar<= 1'b0; //'0' 4'b0111 : tar<= 1'b0 ; //'0' 4'b1000 : tar<= 1'b0 ; //'0' 4'b1001 : tar <= 1'b0; //'1' 4'b1010 : tar<= 1'b0; //'0' 4'b1011 : tar<= 1'b0 ; //'0' 4'b1100 : tar<= 1'b0 ; //'0' 4'b1101 : tar<= 1'b0 ; //'0' 4'b1110 : tar <= 1'b0; //'1' 4'b1111 : tar<= 1'b1; //'0' default: tar<= 1'b0 ; //'0' endcase end end always@(posedge SCK2 or negedge RST)begin if(RST == 1'b0 )begin sel <= selinit_value; end else begin sel[4] <= sel[1] ; //シフト動作を開始する sel[3] <= sel[4] ; //シフト動作を開始する sel[2] <= sel[3] ; //シフト動作を開始する sel[1] <= sel[2] ; end end assign SEL[4:1] = ~sel[4:1]; always@(negedge RST or negedge cn[1]) //* always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[1] or posedge SCK) begin if(RST ==1'b0)begin seven_seg1_hold <=8'b00000110; end else if(cn[1]==1'b0 )begin if(SCK ==1'b1&& WRCYC==1'b1) case(LADCOM) 4'b0000 : seven_seg1_hold<= 8'b00111111 ; //'0' dot g f e d c b a 4'b0001 : seven_seg1_hold <= 8'b00000110 ; //'1' 4'b0010 :seven_seg1_hold<= 8'b01011011 ; //'2' 4'b0011 : seven_seg1_hold <= 8'b01001111 ; //'3' 4'b0100 : seven_seg1_hold <= 8'b01100110 ; //'4' 4'b0101 : seven_seg1_hold <= 8'b01101101 ; //'5' 4'b0110 : seven_seg1_hold <= 8'b01111101 ; //'6' 4'b0111 : seven_seg1_hold <= 8'b00100111 ; //'7' 4'b1000 : seven_seg1_hold <= 8'b01111111 ; //'8' 4'b1001 : seven_seg1_hold <= 8'b01101111 ; //'9' 4'b1010 : seven_seg1_hold <= 8'b01110111 ; //'A' 4'b1011 : seven_seg1_hold <= 8'b01111100 ; //'b' 4'b1100 : seven_seg1_hold <= 8'b01011000 ; //'c' 4'b1101 : seven_seg1_hold <= 8'b01011110 ; //'d' 4'b1110 : seven_seg1_hold <= 8'b01111001 ; //'E' 4'b1111 : seven_seg1_hold <= 8'b01110001 ; //'F' default: seven_seg1_hold <= 8'b01110001; endcase end end always@(negedge RST or negedge cn[2]) //always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[2] or posedge SCK) begin if(RST ==1'b0)begin seven_seg2_hold <=8'b00000110; end else if(cn[2]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1) case(LADCOM) 4'b0000 : seven_seg2_hold<= 8'b00111111 ; //'0 4'b0001 : seven_seg2_hold <= 8'b00000110 ; //'1' 4'b0010 :seven_seg2_hold<= 8'b01011011 ; //'2' 4'b0011 : seven_seg2_hold <= 8'b01001111 ; //'3' 4'b0100 : seven_seg2_hold <= 8'b01100110 ; //'4' 4'b0101 : seven_seg2_hold <= 8'b01101101 ; //'5' 4'b0110 : seven_seg2_hold <= 8'b01111101 ; //'6' 4'b0111 : seven_seg2_hold <= 8'b00100111 ; //'7' 4'b1000 : seven_seg2_hold <= 8'b01111111 ; //'8' 4'b1001 : seven_seg2_hold <= 8'b01101111 ; //'9' 4'b1010 : seven_seg2_hold <= 8'b01110111 ; //'A' 4'b1011 : seven_seg2_hold <= 8'b01111100 ; //'b' 4'b1100 : seven_seg2_hold <= 8'b01011000 ; //'c' 4'b1101 : seven_seg2_hold <= 8'b01011110 ; //'d' 4'b1110 : seven_seg2_hold <= 8'b01111001 ; //'E' 4'b1111 : seven_seg2_hold <= 8'b01110001 ; //'F' default: seven_seg2_hold <= 8'b01110001; endcase end end always@(negedge RST or negedge cn[3]) //always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[3] or posedge SCK) begin if(RST ==1'b0)begin seven_seg3_hold <=8'b00000110; end else if(cn[3]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1 ) case(LADCOM) 4'b0000 : seven_seg3_hold<= 8'b00111111 ; //'0' 4'b0001 : seven_seg3_hold <= 8'b00000110 ; //'1' 4'b0010 :seven_seg3_hold<= 8'b01011011 ; //'2' 4'b0011 : seven_seg3_hold <= 8'b01001111 ; //'3' 4'b0100 : seven_seg3_hold <= 8'b01100110 ; //'4' 4'b0101 : seven_seg3_hold <= 8'b01101101 ; //'5' 4'b0110 : seven_seg3_hold <= 8'b01111101 ; //'6' 4'b0111 : seven_seg3_hold <= 8'b00100111 ; //'7' 4'b1000 : seven_seg3_hold <= 8'b01111111 ; //'8' 4'b1001 : seven_seg3_hold <= 8'b01101111 ; //'9' 4'b1010 : seven_seg3_hold <= 8'b01110111 ; //'A' 4'b1011 : seven_seg3_hold <= 8'b01111100 ; //'b' 4'b1100 : seven_seg3_hold <= 8'b01011000 ; //'c' 4'b1101 : seven_seg3_hold <= 8'b01011110 ; //'d' 4'b1110 : seven_seg3_hold <= 8'b01111001 ; //'E' 4'b1111 : seven_seg3_hold <= 8'b01110001 ; //'F' default: seven_seg3_hold <= 8'b01110001; endcase end end always@(negedge RST or negedge cn[4]) //always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[4] or posedge SCK) begin if(RST ==1'b0)begin seven_seg4_hold <=8'b00000110; end else if(cn[4]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1 ) case(LADCOM) 4'b0000 : seven_seg4_hold<= 8'b00111111 ; //'0' 4'b0001 : seven_seg4_hold <= 8'b00000110 ; //'1' 4'b0010 :seven_seg4_hold<= 8'b01011011 ; //'2' 4'b0011 : seven_seg4_hold <= 8'b01001111 ; //'3' 4'b0100 : seven_seg4_hold <= 8'b01100110 ; //'4' 4'b0101 : seven_seg4_hold <= 8'b01101101 ; //'5' 4'b0110 : seven_seg4_hold <= 8'b01111101 ; //'6' 4'b0111 : seven_seg4_hold <= 8'b00100111 ; //'7' 4'b1000 : seven_seg4_hold <= 8'b01111111 ; //'8' 4'b1001 : seven_seg4_hold <= 8'b01101111 ; //'9' 4'b1010 : seven_seg4_hold <= 8'b01110111 ; //'A' 4'b1011 : seven_seg4_hold <= 8'b01111100 ; //'b' 4'b1100 : seven_seg4_hold <= 8'b01011000 ; //'c' 4'b1101 : seven_seg4_hold <= 8'b01011110 ; //'d' 4'b1110 : seven_seg4_hold <= 8'b01111001 ; //'E' 4'b1111 : seven_seg4_hold <= 8'b01110001 ; //'F' default: seven_seg4_hold <= 8'b01110001; endcase end end always@(negedge RST or negedge cn[1]) begin if(RST ==1'b0)begin ad1 <=4'b0000; end else if(cn[1]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1) ad1 <= LADCOM; end end always@(negedge RST or negedge cn[2]) begin if(RST ==1'b0)begin ad2 <=4'b0000; end else if(cn[2]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1) ad2 <= LADCOM; end end always@(negedge RST or negedge cn[3]) begin if(RST ==1'b0)begin ad3 <=4'b0000; end else if(cn[3]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1) ad3 <= LADCOM; end end always@(negedge RST or negedge cn[4]) begin if(RST ==1'b0)begin ad4 <=4'b0000; end else if(cn[4]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1) ad4 <= LADCOM; end end always@(negedge RST or negedge cn[5]) begin if(RST ==1'b0)begin ad <=16'h0000; end else if(cn[5]==1'b0)begin if(WRCYC==1'b1) ad <={ad1,ad2,ad3,ad4}; end end always@(negedge RST or negedge cn[6]) begin if(RST ==1'b0)begin ld1 <=4'b0000; end else if(cn[6]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1) ld1 <= LADCOM; end end always@(negedge RST or negedge cn[5]) begin if(RST ==1'b0)begin ld2 <=4'b0000; end else if(cn[5]==1'b0)begin if(SCK ==1'b1&& WRCYC==1'b1 ) ld2 <=LADCOM; end end always@(negedge RST or negedge cn[6]) begin if(RST ==1'b0)begin ld <=8'b00000000; end else if(cn[6]==1'b0)begin if(WRCYC==1'b1 && en80 ==1'b1) ld <={ld2,LADCOM}; end end always@(negedge RST or negedge SW1 or negedge cn[7]) begin if(RST ==1'b0)begin en80 <=1'b0; end else if(SW1==1'b0)begin en80 <=1'b0; end else if(WRCYC==1'b1 && ad == 16'h0080)begin en80<=1'b1; end else begin en80<=1'b0; end end always@(posedge SCK2 or negedge RST)begin if(RST == 1'b0 )begin enable_seg <= 2'b00; end else begin enable_seg <= enable_seg +1'b1; end end always@* //* whenever inputs change, holding counter value as the resister "SEVEN_SEG_DATA" begin case(enable_seg) 2'b00: SEVEN_SEG_DATA <= ~seven_seg4_hold; 2'b01: SEVEN_SEG_DATA<=~seven_seg1_hold; 2'b10: SEVEN_SEG_DATA<=~seven_seg2_hold; 2'b11: SEVEN_SEG_DATA<=~seven_seg3_hold; default SEVEN_SEG_DATA<=8'b11111111; endcase end always@(negedge RST or posedge SCK2) begin if(RST == 1'b0 )begin dsel <= dselinit_value; end else begin dsel[2]<=dsel[1] ; //シフト動作を開始する dsel[1] <= dsel[2] ; //シフト動作を開始する end end assign DSEL[2:1] =~dsel[2:1]; always@(negedge RST or posedge en80) //cn6 // always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[5] or posedge SCK) begin if(RST ==1'b0)begin dseven_seg1_hold <=8'b00000110; end else if(en80 == 1'b1 )begin if(SCK ==1'b1 && WRCYC==1'b1 ) case(ld2)//LADCOM 4'b0000 : dseven_seg1_hold<= 8'b00111111 ; //'0' dot g f e d c b a 4'b0001 : dseven_seg1_hold <= 8'b00000110 ; //'1' 4'b0010 : dseven_seg1_hold<= 8'b01011011 ; //'2' 4'b0011 : dseven_seg1_hold <= 8'b01001111 ; //'3' 4'b0100 : dseven_seg1_hold <= 8'b01100110 ; //'4' 4'b0101 : dseven_seg1_hold <= 8'b01101101 ; //'5' 4'b0110 : dseven_seg1_hold <= 8'b01111101 ; //'6' 4'b0111 : dseven_seg1_hold <= 8'b00100111 ; //'7' 4'b1000 : dseven_seg1_hold <= 8'b01111111 ; //'8' 4'b1001 : dseven_seg1_hold <= 8'b01101111 ; //'9' 4'b1010 : dseven_seg1_hold <= 8'b01110111 ; //'A' 4'b1011 : dseven_seg1_hold <= 8'b01111100 ; //'b' 4'b1100 : dseven_seg1_hold <= 8'b01011000 ; //'c' 4'b1101 : dseven_seg1_hold <= 8'b01011110 ; //'d' 4'b1110 : dseven_seg1_hold <= 8'b01111001 ; //'E' 4'b1111 : dseven_seg1_hold <= 8'b01110001 ; //'F' default: dseven_seg1_hold <= 8'b01110001; endcase end end always@(negedge RST or posedge en80) //5 //always@(negedge SW1 or negedge RST or posedge CLK or posedge LADCOM[3:0] or negedge cn[6] or posedge SCK) begin if(RST ==1'b0)begin dseven_seg2_hold <=8'b00000110; end else if(en80 == 1'b1)begin if(SCK ==1'b1 && WRCYC==1'b1 ) case(ld1) 4'b0000 : dseven_seg2_hold<= 8'b00111111 ; //'0 4'b0001 : dseven_seg2_hold <= 8'b00000110 ; //'1' 4'b0010 : dseven_seg2_hold<= 8'b01011011 ; //'2' 4'b0011 : dseven_seg2_hold <= 8'b01001111 ; //'3' 4'b0100 : dseven_seg2_hold <= 8'b01100110 ; //'4' 4'b0101 : dseven_seg2_hold <= 8'b01101101 ; //'5' 4'b0110 : dseven_seg2_hold <= 8'b01111101 ; //'6' 4'b0111 : dseven_seg2_hold <= 8'b00100111 ; //'7' 4'b1000 : dseven_seg2_hold <= 8'b01111111 ; //'8' 4'b1001 : dseven_seg2_hold <= 8'b01101111 ; //'9' 4'b1010 : dseven_seg2_hold <= 8'b01110111 ; //'A' 4'b1011 : dseven_seg2_hold <= 8'b01111100 ; //'b' 4'b1100 : dseven_seg2_hold <= 8'b01011000 ; //'c' 4'b1101 : dseven_seg2_hold <= 8'b01011110 ; //'d' 4'b1110 : dseven_seg2_hold <= 8'b01111001 ; //'E' 4'b1111 : dseven_seg2_hold <= 8'b01110001 ; //'F' default: dseven_seg2_hold <= 8'b01110001; endcase end end always@(posedge SCK2 or negedge RST)begin if(RST == 1'b0 )begin denable_seg <= 1'b0; end else begin denable_seg <= denable_seg +1'b1; end end always@* //* whenever inputs change, holding counter value as the resister "SEVEN_SEG_DATA" begin case(denable_seg) 1'b0: DSEVEN_SEG_DATA <= ~dseven_seg2_hold; 1'b1: DSEVEN_SEG_DATA<=~dseven_seg1_hold; default DSEVEN_SEG_DATA<=8'b11111111; endcase end // assign SEVEN_SEG_DATA = seven_seg_data; endmodule
`timescale 1 ns/ 1 ns module LPC_PORT80h_decoder7_vlg_tst(); // constants // general purpose registers reg eachvec; // test vector input registers reg CLK; reg [3:0] LADCOM; reg RST; reg SW1; // wires wire [3:0] COMOUT; wire [4:0] CS_COUNTER; wire [2:1] DSEL; wire [7:0] DSEVEN_SEG_DATA; wire NFRAME; wire [16:0] NRCOUNTER; wire NSCK; wire SCK; wire SCK2; wire [4:1] SEL; wire [7:0] SEVEN_SEG_DATA; wire WRCYC; parameter STEP1 = 500; // ns parameter STEP2 = 10; //ns 33MHz // assign statements (if any) LPC_PORT80h_decoder7 i1 ( // port map - connection between master ports and signals/registers .CLK(CLK), .COMOUT(COMOUT), .CS_COUNTER(CS_COUNTER), .DSEL(DSEL), .DSEVEN_SEG_DATA(DSEVEN_SEG_DATA), .LADCOM(LADCOM), .NFRAME(NFRAME), .NRCOUNTER(NRCOUNTER), .NSCK(NSCK), .RST(RST), .SCK(SCK), .SCK2(SCK2), .SEL(SEL), .SEVEN_SEG_DATA(SEVEN_SEG_DATA), .SW1(SW1), .WRCYC(WRCYC) ); initial begin RST <=1'b0; CLK <=1'b0; SW1 <= 1'b1; //1 //RST deassert SW1(frame) assert addr 80h data 5Ah #1 SW1 <= 1'b0; #0 RST <= 1'b1; #9 SW1 <=1'b1; #0 LADCOM[3:0] <=4'b0010; #10 LADCOM[3:0] <=4'b0000;//0x0 #10 LADCOM[3:0] <=4'b0000;//0x0 #10 LADCOM[3:0] <=4'b1000;//0x8 #10 LADCOM[3:0] <=4'b0000;//0x0 #10 LADCOM[3:0] <=4'b1010;//0xA #10 LADCOM[3:0] <=4'b0101;//0x5 #10 LADCOM[3:0] <=4'b0001;//0x1 #10 LADCOM[3:0] <=4'b0010;//0x2 #10 LADCOM[3:0] <=4'b0100;//0x8 #10 LADCOM[3:0] <=4'b1111;//0xf //RST deassert SW1(frame) assert addr 1248h data 21h #10 RST <= 1'b0; #10 RST <= 1'b1; #10 SW1 <= 1'b0; #10 SW1 <=1'b1; #0 LADCOM[3:0] <=4'b0010; //0x0 #10 LADCOM[3:0] <=4'b0001;//0x1 #10 LADCOM[3:0] <=4'b0010;//0x2 #10 LADCOM[3:0] <=4'b0100;//0x4 #10 LADCOM[3:0] <=4'b0000;//0x8 #10 LADCOM[3:0] <=4'b0000;//0x1 #10 LADCOM[3:0] <=4'b0010;//0x2 #10 LADCOM[3:0] <=4'b0001; #10 LADCOM[3:0] <=4'b0010; #10 LADCOM[3:0] <=4'b0100; #10 LADCOM[3:0] <=4'b1111; //SW1(frame) assert addr 1248h data 21h #10 SW1 <= 1'b0; #10 SW1 <=1'b1; #0 LADCOM[3:0] <=4'b0000; //0x0 #10 LADCOM[3:0] <=4'b0001;//0x1 #10 LADCOM[3:0] <=4'b0010;//0x2 #10 LADCOM[3:0] <=4'b0100;//0x4 #10 LADCOM[3:0] <=4'b0000;//0x8 #10 LADCOM[3:0] <=4'b0000;//0x1 #10 LADCOM[3:0] <=4'b0010;//0x2 #10 LADCOM[3:0] <=4'b0001; #10 LADCOM[3:0] <=4'b0010; #10 LADCOM[3:0] <=4'b0100; #10 LADCOM[3:0] <=4'b1111; //SW1(frame) assert addr 0080h data bah #10 SW1 <= 1'b0; #10 SW1 <=1'b1; #0 LADCOM[3:0] <=4'b0010; //0x2 #10 LADCOM[3:0] <=4'b0000;//0x0 #10 LADCOM[3:0] <=4'b0000;//0x0 #10 LADCOM[3:0] <=4'b1000;//0x8 #10 LADCOM[3:0] <=4'b0000;//0x0 #10 LADCOM[3:0] <=4'b1010;//0xa #10 LADCOM[3:0] <=4'b1011;//0xb #10 LADCOM[3:0] <=4'b1100;//0xc #10 LADCOM[3:0] <=4'b1101;//0xd #10 LADCOM[3:0] <=4'b1110;//0xe #10 LADCOM[3:0] <=4'b1111;//0xf // code that executes only once // insert code here --> begin // --> end $display("Running testbench"); end //always#(STEP1/2) //begin //RST <= ~RST; //end always#(STEP2/2) begin CLK <= ~CLK; end // optional sensitivity list // @(event1 or event2 or .... eventn) //begin // code executes for every event on sensitivity list // insert code here --> begin //@eachvec; // --> end //end endmodule